testlist.vo

有用的verilog hdl实验用程序 配有截图

	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr2~50 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr2~50_I .clock_enable_mode = "false";
defparam \WideOr2~50_I .lut_mask = "0008";
defparam \WideOr2~50_I .operation_mode = "normal";
defparam \WideOr2~50_I .output_mode = "comb_only";
defparam \WideOr2~50_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC6_C21
flex10ke_lcell \WideOr1~186_I (
// Equation(s):
// \WideOr1~186  = !\list~dataout [4] & !\list~dataout [1] & !\list~dataout [2] & !\list~dataout [3]

	.dataa(\list~dataout [4]),
	.datab(\list~dataout [1]),
	.datac(\list~dataout [2]),
	.datad(\list~dataout [3]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr1~186 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr1~186_I .clock_enable_mode = "false";
defparam \WideOr1~186_I .lut_mask = "0001";
defparam \WideOr1~186_I .operation_mode = "normal";
defparam \WideOr1~186_I .output_mode = "comb_only";
defparam \WideOr1~186_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC2_C21
flex10ke_lcell \WideOr0~138_I (
// Equation(s):
// \WideOr0~138  = \WideOr1~186  & !\list~dataout [5] & !\list~dataout [6]

	.dataa(vcc),
	.datab(\WideOr1~186 ),
	.datac(\list~dataout [5]),
	.datad(\list~dataout [6]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr0~138 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr0~138_I .clock_enable_mode = "false";
defparam \WideOr0~138_I .lut_mask = "000C";
defparam \WideOr0~138_I .operation_mode = "normal";
defparam \WideOr0~138_I .output_mode = "comb_only";
defparam \WideOr0~138_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC1_C27
flex10ke_lcell \WideOr1~187_I (
// Equation(s):
// \WideOr1~187  = \list~dataout [1] & !\list~dataout [2] & !\list~dataout [3] & !\list~dataout [4] # !\list~dataout [1] & (\list~dataout [2] & !\list~dataout [3] & !\list~dataout [4] # !\list~dataout [2] & (\list~dataout [3] $ \list~dataout [4]))

	.dataa(\list~dataout [1]),
	.datab(\list~dataout [2]),
	.datac(\list~dataout [3]),
	.datad(\list~dataout [4]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr1~187 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr1~187_I .clock_enable_mode = "false";
defparam \WideOr1~187_I .lut_mask = "0116";
defparam \WideOr1~187_I .operation_mode = "normal";
defparam \WideOr1~187_I .output_mode = "comb_only";
defparam \WideOr1~187_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC1_C21
flex10ke_lcell \WideOr1~188_I (
// Equation(s):
// \WideOr1~188  = \list~dataout [5] & \WideOr1~186  & (!\list~dataout [6]) # !\list~dataout [5] & (\list~dataout [6] & \WideOr1~186  # !\list~dataout [6] & (\WideOr1~187 ))

	.dataa(\WideOr1~186 ),
	.datab(\WideOr1~187 ),
	.datac(\list~dataout [5]),
	.datad(\list~dataout [6]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr1~188 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr1~188_I .clock_enable_mode = "false";
defparam \WideOr1~188_I .lut_mask = "0AAC";
defparam \WideOr1~188_I .operation_mode = "normal";
defparam \WideOr1~188_I .output_mode = "comb_only";
defparam \WideOr1~188_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_C27
flex10ke_lcell \WideOr1~189_I (
// Equation(s):
// \WideOr1~189  = !\list~dataout [8] & (\list~dataout [7] & \WideOr0~138  # !\list~dataout [7] & (\WideOr1~188 ))

	.dataa(\WideOr0~138 ),
	.datab(\WideOr1~188 ),
	.datac(\list~dataout [7]),
	.datad(\list~dataout [8]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr1~189 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr1~189_I .clock_enable_mode = "false";
defparam \WideOr1~189_I .lut_mask = "00AC";
defparam \WideOr1~189_I .operation_mode = "normal";
defparam \WideOr1~189_I .output_mode = "comb_only";
defparam \WideOr1~189_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC1_C34
flex10ke_lcell \WideOr0~139_I (
// Equation(s):
// \WideOr0~139  = \list~dataout [8] & \WideOr0~138  & (!\list~dataout [7]) # !\list~dataout [8] & (\list~dataout [7] & \WideOr0~138  # !\list~dataout [7] & (\WideOr1~188 ))

	.dataa(\WideOr0~138 ),
	.datab(\WideOr1~188 ),
	.datac(\list~dataout [8]),
	.datad(\list~dataout [7]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr0~139 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr0~139_I .clock_enable_mode = "false";
defparam \WideOr0~139_I .lut_mask = "0AAC";
defparam \WideOr0~139_I .operation_mode = "normal";
defparam \WideOr0~139_I .output_mode = "comb_only";
defparam \WideOr0~139_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC3_C21
flex10ke_lcell \WideOr0~142_I (
// Equation(s):
// \WideOr0~142  = \list~dataout [8] & \WideOr0~138  & (!\list~dataout [7]) # !\list~dataout [8] & (\list~dataout [7] & \WideOr0~138  # !\list~dataout [7] & (\WideOr1~188 ))

	.dataa(\WideOr0~138 ),
	.datab(\WideOr1~188 ),
	.datac(\list~dataout [8]),
	.datad(\list~dataout [7]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr0~142 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr0~142_I .clock_enable_mode = "false";
defparam \WideOr0~142_I .lut_mask = "0AAC";
defparam \WideOr0~142_I .operation_mode = "normal";
defparam \WideOr0~142_I .output_mode = "comb_only";
defparam \WideOr0~142_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_C26
flex10ke_lcell \WideOr0~143_I (
// Equation(s):
// \WideOr0~143  = \list~dataout [8] & \WideOr0~138  & (!\list~dataout [7]) # !\list~dataout [8] & (\list~dataout [7] & \WideOr0~138  # !\list~dataout [7] & (\WideOr1~188 ))

	.dataa(\WideOr0~138 ),
	.datab(\WideOr1~188 ),
	.datac(\list~dataout [8]),
	.datad(\list~dataout [7]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr0~143 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr0~143_I .clock_enable_mode = "false";
defparam \WideOr0~143_I .lut_mask = "0AAC";
defparam \WideOr0~143_I .operation_mode = "normal";
defparam \WideOr0~143_I .output_mode = "comb_only";
defparam \WideOr0~143_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_C29
flex10ke_lcell \WideOr0~144_I (
// Equation(s):
// \WideOr0~144  = \list~dataout [8] & \WideOr0~138  & (!\list~dataout [7]) # !\list~dataout [8] & (\list~dataout [7] & \WideOr0~138  # !\list~dataout [7] & (\WideOr1~188 ))

	.dataa(\WideOr0~138 ),
	.datab(\WideOr1~188 ),
	.datac(\list~dataout [8]),
	.datad(\list~dataout [7]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr0~144 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr0~144_I .clock_enable_mode = "false";
defparam \WideOr0~144_I .lut_mask = "0AAC";
defparam \WideOr0~144_I .operation_mode = "normal";
defparam \WideOr0~144_I .output_mode = "comb_only";
defparam \WideOr0~144_I .packed_mode = "false";
// synopsys translate_on

// atom is at PIN_20
flex10ke_io \result[1]~I (
	.datain(!\WideOr4~48 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[1]));
// synopsys translate_off
defparam \result[1]~I .feedback_mode = "none";
defparam \result[1]~I .operation_mode = "output";
defparam \result[1]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_21
flex10ke_io \result[2]~I (
	.datain(!\WideOr3~51 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[2]));
// synopsys translate_off
defparam \result[2]~I .feedback_mode = "none";
defparam \result[2]~I .operation_mode = "output";
defparam \result[2]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_22
flex10ke_io \result[3]~I (
	.datain(!\WideOr2~50 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[3]));
// synopsys translate_off
defparam \result[3]~I .feedback_mode = "none";
defparam \result[3]~I .operation_mode = "output";
defparam \result[3]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_23
flex10ke_io \result[4]~I (
	.datain(!\WideOr1~189 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[4]));
// synopsys translate_off
defparam \result[4]~I .feedback_mode = "none";
defparam \result[4]~I .operation_mode = "output";
defparam \result[4]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_26
flex10ke_io \result[5]~I (
	.datain(!\WideOr0~139 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[5]));
// synopsys translate_off
defparam \result[5]~I .feedback_mode = "none";
defparam \result[5]~I .operation_mode = "output";
defparam \result[5]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_27
flex10ke_io \result[6]~I (
	.datain(!\WideOr0~142 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[6]));
// synopsys translate_off
defparam \result[6]~I .feedback_mode = "none";
defparam \result[6]~I .operation_mode = "output";
defparam \result[6]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_28
flex10ke_io \result[7]~I (
	.datain(!\WideOr0~143 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[7]));
// synopsys translate_off
defparam \result[7]~I .feedback_mode = "none";
defparam \result[7]~I .operation_mode = "output";
defparam \result[7]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_29
flex10ke_io \result[8]~I (
	.datain(!\WideOr0~144 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(result[8]));
// synopsys translate_off
defparam \result[8]~I .feedback_mode = "none";
defparam \result[8]~I .operation_mode = "output";
defparam \result[8]~I .reg_source_mode = "none";
// synopsys translate_on

endmodule