testlist.vo

有用的verilog hdl实验用程序 配有截图

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "05/18/2008 10:09:12"

// 
// Device: Altera EP1K30TC144-3 Package TQFP144
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module testlist (
	list,
	result);
input 	[8:1] list;
output 	[8:1] result;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("testlist_v.sdo");
// synopsys translate_on

wire \WideOr2~48 ;
wire \WideOr4~47 ;
wire \WideOr4~48 ;
wire \WideOr3~49 ;
wire \WideOr3~50 ;
wire \WideOr3~51 ;
wire \WideOr2~49 ;
wire \WideOr2~50 ;
wire \WideOr1~186 ;
wire \WideOr0~138 ;
wire \WideOr1~187 ;
wire \WideOr1~188 ;
wire \WideOr1~189 ;
wire \WideOr0~139 ;
wire \WideOr0~142 ;
wire \WideOr0~143 ;
wire \WideOr0~144 ;
wire [8:1] \list~dataout ;


// atom is at PIN_18
flex10ke_io \list[7]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [7]),
	.padio(list[7]));
// synopsys translate_off
defparam \list[7]~I .feedback_mode = "from_pin";
defparam \list[7]~I .operation_mode = "input";
defparam \list[7]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_13
flex10ke_io \list[5]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [5]),
	.padio(list[5]));
// synopsys translate_off
defparam \list[5]~I .feedback_mode = "from_pin";
defparam \list[5]~I .operation_mode = "input";
defparam \list[5]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at LC5_C21
flex10ke_lcell \WideOr2~48_I (
// Equation(s):
// \WideOr2~48  = !\list~dataout [7] & !\list~dataout [5]

	.dataa(vcc),
	.datab(vcc),
	.datac(\list~dataout [7]),
	.datad(\list~dataout [5]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr2~48 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr2~48_I .clock_enable_mode = "false";
defparam \WideOr2~48_I .lut_mask = "000F";
defparam \WideOr2~48_I .operation_mode = "normal";
defparam \WideOr2~48_I .output_mode = "comb_only";
defparam \WideOr2~48_I .packed_mode = "false";
// synopsys translate_on

// atom is at PIN_9
flex10ke_io \list[2]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [2]),
	.padio(list[2]));
// synopsys translate_off
defparam \list[2]~I .feedback_mode = "from_pin";
defparam \list[2]~I .operation_mode = "input";
defparam \list[2]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_17
flex10ke_io \list[6]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [6]),
	.padio(list[6]));
// synopsys translate_off
defparam \list[6]~I .feedback_mode = "from_pin";
defparam \list[6]~I .operation_mode = "input";
defparam \list[6]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_12
flex10ke_io \list[4]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [4]),
	.padio(list[4]));
// synopsys translate_off
defparam \list[4]~I .feedback_mode = "from_pin";
defparam \list[4]~I .operation_mode = "input";
defparam \list[4]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at LC5_C27
flex10ke_lcell \WideOr4~47_I (
// Equation(s):
// \WideOr4~47  = \list~dataout [8] & !\list~dataout [2] & !\list~dataout [6] & !\list~dataout [4] # !\list~dataout [8] & (\list~dataout [2] & !\list~dataout [6] & !\list~dataout [4] # !\list~dataout [2] & (\list~dataout [6] $ \list~dataout [4]))

	.dataa(\list~dataout [8]),
	.datab(\list~dataout [2]),
	.datac(\list~dataout [6]),
	.datad(\list~dataout [4]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr4~47 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr4~47_I .clock_enable_mode = "false";
defparam \WideOr4~47_I .lut_mask = "0116";
defparam \WideOr4~47_I .operation_mode = "normal";
defparam \WideOr4~47_I .output_mode = "comb_only";
defparam \WideOr4~47_I .packed_mode = "false";
// synopsys translate_on

// atom is at PIN_8
flex10ke_io \list[1]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [1]),
	.padio(list[1]));
// synopsys translate_off
defparam \list[1]~I .feedback_mode = "from_pin";
defparam \list[1]~I .operation_mode = "input";
defparam \list[1]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_10
flex10ke_io \list[3]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [3]),
	.padio(list[3]));
// synopsys translate_off
defparam \list[3]~I .feedback_mode = "from_pin";
defparam \list[3]~I .operation_mode = "input";
defparam \list[3]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at LC2_C27
flex10ke_lcell \WideOr4~48_I (
// Equation(s):
// \WideOr4~48  = \WideOr2~48  & \WideOr4~47  & !\list~dataout [1] & !\list~dataout [3]

	.dataa(\WideOr2~48 ),
	.datab(\WideOr4~47 ),
	.datac(\list~dataout [1]),
	.datad(\list~dataout [3]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr4~48 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr4~48_I .clock_enable_mode = "false";
defparam \WideOr4~48_I .lut_mask = "0008";
defparam \WideOr4~48_I .operation_mode = "normal";
defparam \WideOr4~48_I .output_mode = "comb_only";
defparam \WideOr4~48_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC4_C27
flex10ke_lcell \WideOr3~49_I (
// Equation(s):
// \WideOr3~49  = !\list~dataout [2] & !\list~dataout [3]

	.dataa(vcc),
	.datab(vcc),
	.datac(\list~dataout [2]),
	.datad(\list~dataout [3]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr3~49 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr3~49_I .clock_enable_mode = "false";
defparam \WideOr3~49_I .lut_mask = "000F";
defparam \WideOr3~49_I .operation_mode = "normal";
defparam \WideOr3~49_I .output_mode = "comb_only";
defparam \WideOr3~49_I .packed_mode = "false";
// synopsys translate_on

// atom is at PIN_19
flex10ke_io \list[8]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\list~dataout [8]),
	.padio(list[8]));
// synopsys translate_off
defparam \list[8]~I .feedback_mode = "from_pin";
defparam \list[8]~I .operation_mode = "input";
defparam \list[8]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at LC3_C27
flex10ke_lcell \WideOr3~50_I (
// Equation(s):
// \WideOr3~50  = \list~dataout [1] & !\list~dataout [5] & !\list~dataout [8] & !\list~dataout [4] # !\list~dataout [1] & (\list~dataout [5] & !\list~dataout [8] & !\list~dataout [4] # !\list~dataout [5] & (\list~dataout [8] $ \list~dataout [4]))

	.dataa(\list~dataout [1]),
	.datab(\list~dataout [5]),
	.datac(\list~dataout [8]),
	.datad(\list~dataout [4]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr3~50 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr3~50_I .clock_enable_mode = "false";
defparam \WideOr3~50_I .lut_mask = "0116";
defparam \WideOr3~50_I .operation_mode = "normal";
defparam \WideOr3~50_I .output_mode = "comb_only";
defparam \WideOr3~50_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC4_C21
flex10ke_lcell \WideOr3~51_I (
// Equation(s):
// \WideOr3~51  = \WideOr3~49  & \WideOr3~50  & !\list~dataout [7] & !\list~dataout [6]

	.dataa(\WideOr3~49 ),
	.datab(\WideOr3~50 ),
	.datac(\list~dataout [7]),
	.datad(\list~dataout [6]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr3~51 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr3~51_I .clock_enable_mode = "false";
defparam \WideOr3~51_I .lut_mask = "0008";
defparam \WideOr3~51_I .operation_mode = "normal";
defparam \WideOr3~51_I .output_mode = "comb_only";
defparam \WideOr3~51_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC8_C27
flex10ke_lcell \WideOr2~49_I (
// Equation(s):
// \WideOr2~49  = \list~dataout [1] & !\list~dataout [2] & !\list~dataout [3] & !\list~dataout [8] # !\list~dataout [1] & (\list~dataout [2] & !\list~dataout [3] & !\list~dataout [8] # !\list~dataout [2] & (\list~dataout [3] $ \list~dataout [8]))

	.dataa(\list~dataout [1]),
	.datab(\list~dataout [2]),
	.datac(\list~dataout [3]),
	.datad(\list~dataout [8]),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\WideOr2~49 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \WideOr2~49_I .clock_enable_mode = "false";
defparam \WideOr2~49_I .lut_mask = "0116";
defparam \WideOr2~49_I .operation_mode = "normal";
defparam \WideOr2~49_I .output_mode = "comb_only";
defparam \WideOr2~49_I .packed_mode = "false";
// synopsys translate_on

// atom is at LC6_C27
flex10ke_lcell \WideOr2~50_I (
// Equation(s):
// \WideOr2~50  = \WideOr2~48  & \WideOr2~49  & !\list~dataout [6] & !\list~dataout [4]

	.dataa(\WideOr2~48 ),
	.datab(\WideOr2~49 ),
	.datac(\list~dataout [6]),
	.datad(\list~dataout [4]),
	.aclr(gnd),