alarm_clock.tan.qmsg

来自「可以调整时间和设置闹钟的数字钟(VHDL)」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "key_down register register key_buffer:u2\|n_t\[2\]\[0\] key_buffer:u2\|n_t\[3\]\[0\] 275.03 MHz Internal " "Info: Clock \"key_down\" Internal fmax is restricted to 275.03 MHz between source register \"key_buffer:u2\|n_t\[2\]\[0\]\" and destination register \"key_buffer:u2\|n_t\[3\]\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.958 ns + Longest register register " "Info: + Longest register to register delay is 0.958 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_buffer:u2\|n_t\[2\]\[0\] 1 REG LC_X11_Y8_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y8_N3; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[2\]\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_buffer:u2|n_t[2][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.843 ns) + CELL(0.115 ns) 0.958 ns key_buffer:u2\|n_t\[3\]\[0\] 2 REG LC_X11_Y8_N1 5 " "Info: 2: + IC(0.843 ns) + CELL(0.115 ns) = 0.958 ns; Loc. = LC_X11_Y8_N1; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[3\]\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.958 ns" { key_buffer:u2|n_t[2][0] key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 12.00 % ) " "Info: Total cell delay = 0.115 ns ( 12.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.843 ns ( 88.00 % ) " "Info: Total interconnect delay = 0.843 ns ( 88.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.958 ns" { key_buffer:u2|n_t[2][0] key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.958 ns" { key_buffer:u2|n_t[2][0] key_buffer:u2|n_t[3][0] } { 0.000ns 0.843ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key_down destination 7.322 ns + Shortest register " "Info: + Shortest clock path from clock \"key_down\" to destination register is 7.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_down 1 CLK PIN_48 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 33; CLK Node = 'key_down'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.142 ns) + CELL(0.711 ns) 7.322 ns key_buffer:u2\|n_t\[3\]\[0\] 2 REG LC_X11_Y8_N1 5 " "Info: 2: + IC(5.142 ns) + CELL(0.711 ns) = 7.322 ns; Loc. = LC_X11_Y8_N1; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[3\]\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.853 ns" { key_down key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.77 % ) " "Info: Total cell delay = 2.180 ns ( 29.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.142 ns ( 70.23 % ) " "Info: Total interconnect delay = 5.142 ns ( 70.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[3][0] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key_down source 7.322 ns - Longest register " "Info: - Longest clock path from clock \"key_down\" to source register is 7.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_down 1 CLK PIN_48 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 33; CLK Node = 'key_down'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.142 ns) + CELL(0.711 ns) 7.322 ns key_buffer:u2\|n_t\[2\]\[0\] 2 REG LC_X11_Y8_N3 5 " "Info: 2: + IC(5.142 ns) + CELL(0.711 ns) = 7.322 ns; Loc. = LC_X11_Y8_N3; Fanout = 5; REG Node = 'key_buffer:u2\|n_t\[2\]\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.853 ns" { key_down key_buffer:u2|n_t[2][0] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.77 % ) " "Info: Total cell delay = 2.180 ns ( 29.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.142 ns ( 70.23 % ) " "Info: Total interconnect delay = 5.142 ns ( 70.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[2][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[2][0] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[3][0] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[2][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[2][0] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.958 ns" { key_buffer:u2|n_t[2][0] key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.958 ns" { key_buffer:u2|n_t[2][0] key_buffer:u2|n_t[3][0] } { 0.000ns 0.843ns } { 0.000ns 0.115ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[3][0] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[2][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[2][0] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_buffer:u2|n_t[3][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { key_buffer:u2|n_t[3][0] } {  } {  } "" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "led_display:U8\|clock_out\[6\] alarm_button clk 10.124 ns register " "Info: tsu for register \"led_display:U8\|clock_out\[6\]\" (data pin = \"alarm_button\", clock pin = \"clk\") is 10.124 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "17.773 ns + Longest pin register " "Info: + Longest pin to register delay is 17.773 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns alarm_button 1 PIN PIN_2 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_2; Fanout = 8; PIN Node = 'alarm_button'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { alarm_button } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.415 ns) + CELL(0.590 ns) 9.474 ns alarm_controller:u3\|Selector4~22 2 COMB LC_X11_Y8_N7 49 " "Info: 2: + IC(7.415 ns) + CELL(0.590 ns) = 9.474 ns; Loc. = LC_X11_Y8_N7; Fanout = 49; COMB Node = 'alarm_controller:u3\|Selector4~22'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.005 ns" { alarm_button alarm_controller:u3|Selector4~22 } "NODE_NAME" } } { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 52 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.703 ns) + CELL(0.442 ns) 11.619 ns display_driver:u6\|display_time\[1\]\[0\]~5014 3 COMB LC_X13_Y9_N4 1 " "Info: 3: + IC(1.703 ns) + CELL(0.442 ns) = 11.619 ns; Loc. = LC_X13_Y9_N4; Fanout = 1; COMB Node = 'display_driver:u6\|display_time\[1\]\[0\]~5014'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.145 ns" { alarm_controller:u3|Selector4~22 display_driver:u6|display_time[1][0]~5014 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.114 ns) 13.273 ns display_driver:u6\|display_time\[1\]\[0\]~5015 4 COMB LC_X11_Y8_N9 7 " "Info: 4: + IC(1.540 ns) + CELL(0.114 ns) = 13.273 ns; Loc. = LC_X11_Y8_N9; Fanout = 7; COMB Node = 'display_driver:u6\|display_time\[1\]\[0\]~5015'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.654 ns" { display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.315 ns) + CELL(0.114 ns) 14.702 ns display_driver:u6\|Mux7~32 5 COMB LC_X12_Y9_N4 1 " "Info: 5: + IC(1.315 ns) + CELL(0.114 ns) = 14.702 ns; Loc. = LC_X12_Y9_N4; Fanout = 1; COMB Node = 'display_driver:u6\|Mux7~32'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.429 ns" { display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.114 ns) 16.042 ns led_display:U8\|Mux0~317 6 COMB LC_X12_Y8_N4 1 " "Info: 6: + IC(1.226 ns) + CELL(0.114 ns) = 16.042 ns; Loc. = LC_X12_Y8_N4; Fanout = 1; COMB Node = 'led_display:U8\|Mux0~317'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.340 ns" { display_driver:u6|Mux7~32 led_display:U8|Mux0~317 } "NODE_NAME" } } { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.478 ns) 17.773 ns led_display:U8\|clock_out\[6\] 7 REG LC_X11_Y9_N3 1 " "Info: 7: + IC(1.253 ns) + CELL(0.478 ns) = 17.773 ns; Loc. = LC_X11_Y9_N3; Fanout = 1; REG Node = 'led_display:U8\|clock_out\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.731 ns" { led_display:U8|Mux0~317 led_display:U8|clock_out[6] } "NODE_NAME" } } { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.321 ns ( 18.69 % ) " "Info: Total cell delay = 3.321 ns ( 18.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.452 ns ( 81.31 % ) " "Info: Total interconnect delay = 14.452 ns ( 81.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "17.773 ns" { alarm_button alarm_controller:u3|Selector4~22 display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "17.773 ns" { alarm_button alarm_button~out0 alarm_controller:u3|Selector4~22 display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 7.415ns 1.703ns 1.540ns 1.315ns 1.226ns 1.253ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.114ns 0.114ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.686 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_3 90 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 90; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.506 ns) + CELL(0.711 ns) 7.686 ns led_display:U8\|clock_out\[6\] 2 REG LC_X11_Y9_N3 1 " "Info: 2: + IC(5.506 ns) + CELL(0.711 ns) = 7.686 ns; Loc. = LC_X11_Y9_N3; Fanout = 1; REG Node = 'led_display:U8\|clock_out\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.217 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.36 % ) " "Info: Total cell delay = 2.180 ns ( 28.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.506 ns ( 71.64 % ) " "Info: Total interconnect delay = 5.506 ns ( 71.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "17.773 ns" { alarm_button alarm_controller:u3|Selector4~22 display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "17.773 ns" { alarm_button alarm_button~out0 alarm_controller:u3|Selector4~22 display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 7.415ns 1.703ns 1.540ns 1.315ns 1.226ns 1.253ns } { 0.000ns 1.469ns 0.590ns 0.442ns 0.114ns 0.114ns 0.114ns 0.478ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "key_down sound_alarm key_buffer:u2\|n_t\[5\]\[3\] 18.176 ns register " "Info: tco from clock \"key_down\" to destination pin \"sound_alarm\" through register \"key_buffer:u2\|n_t\[5\]\[3\]\" is 18.176 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "key_down source 7.322 ns + Longest register " "Info: + Longest clock path from clock \"key_down\" to source register is 7.322 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_down 1 CLK PIN_48 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 33; CLK Node = 'key_down'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.142 ns) + CELL(0.711 ns) 7.322 ns key_buffer:u2\|n_t\[5\]\[3\] 2 REG LC_X10_Y9_N7 4 " "Info: 2: + IC(5.142 ns) + CELL(0.711 ns) = 7.322 ns; Loc. = LC_X10_Y9_N7; Fanout = 4; REG Node = 'key_buffer:u2\|n_t\[5\]\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.853 ns" { key_down key_buffer:u2|n_t[5][3] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 29.77 % ) " "Info: Total cell delay = 2.180 ns ( 29.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.142 ns ( 70.23 % ) " "Info: Total interconnect delay = 5.142 ns ( 70.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[5][3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[5][3] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.630 ns + Longest register pin " "Info: + Longest register to pin delay is 10.630 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns key_buffer:u2\|n_t\[5\]\[3\] 1 REG LC_X10_Y9_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y9_N7; Fanout = 4; REG Node = 'key_buffer:u2\|n_t\[5\]\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_buffer:u2|n_t[5][3] } "NODE_NAME" } } { "key_buffer.vhd" "" { Text "E:/PLDS/CLOCK/key_buffer.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.377 ns) + CELL(0.442 ns) 2.819 ns display_driver:u6\|ctrl~240 2 COMB LC_X13_Y10_N9 1 " "Info: 2: + IC(2.377 ns) + CELL(0.442 ns) = 2.819 ns; Loc. = LC_X13_Y10_N9; Fanout = 1; COMB Node = 'display_driver:u6\|ctrl~240'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.819 ns" { key_buffer:u2|n_t[5][3] display_driver:u6|ctrl~240 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.838 ns) + CELL(0.590 ns) 5.247 ns display_driver:u6\|ctrl~243 3 COMB LC_X9_Y7_N4 1 " "Info: 3: + IC(1.838 ns) + CELL(0.590 ns) = 5.247 ns; Loc. = LC_X9_Y7_N4; Fanout = 1; COMB Node = 'display_driver:u6\|ctrl~243'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.428 ns" { display_driver:u6|ctrl~240 display_driver:u6|ctrl~243 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.442 ns) 6.089 ns display_driver:u6\|ctrl~249 4 COMB LC_X9_Y7_N6 1 " "Info: 4: + IC(0.400 ns) + CELL(0.442 ns) = 6.089 ns; Loc. = LC_X9_Y7_N6; Fanout = 1; COMB Node = 'display_driver:u6\|ctrl~249'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.842 ns" { display_driver:u6|ctrl~243 display_driver:u6|ctrl~249 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.433 ns) + CELL(2.108 ns) 10.630 ns sound_alarm 5 PIN PIN_62 0 " "Info: 5: + IC(2.433 ns) + CELL(2.108 ns) = 10.630 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'sound_alarm'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.541 ns" { display_driver:u6|ctrl~249 sound_alarm } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.582 ns ( 33.70 % ) " "Info: Total cell delay = 3.582 ns ( 33.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.048 ns ( 66.30 % ) " "Info: Total interconnect delay = 7.048 ns ( 66.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.630 ns" { key_buffer:u2|n_t[5][3] display_driver:u6|ctrl~240 display_driver:u6|ctrl~243 display_driver:u6|ctrl~249 sound_alarm } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.630 ns" { key_buffer:u2|n_t[5][3] display_driver:u6|ctrl~240 display_driver:u6|ctrl~243 display_driver:u6|ctrl~249 sound_alarm } { 0.000ns 2.377ns 1.838ns 0.400ns 2.433ns } { 0.000ns 0.442ns 0.590ns 0.442ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.322 ns" { key_down key_buffer:u2|n_t[5][3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.322 ns" { key_down key_down~out0 key_buffer:u2|n_t[5][3] } { 0.000ns 0.000ns 5.142ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "10.630 ns" { key_buffer:u2|n_t[5][3] display_driver:u6|ctrl~240 display_driver:u6|ctrl~243 display_driver:u6|ctrl~249 sound_alarm } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "10.630 ns" { key_buffer:u2|n_t[5][3] display_driver:u6|ctrl~240 display_driver:u6|ctrl~243 display_driver:u6|ctrl~249 sound_alarm } { 0.000ns 2.377ns 1.838ns 0.400ns 2.433ns } { 0.000ns 0.442ns 0.590ns 0.442ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}