alarm_clock.tan.qmsg

来自「可以调整时间和设置闹钟的数字钟(VHDL)」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 11 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "key_down " "Info: Assuming node \"key_down\" is an undefined clock" {  } { { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 8 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "key_down" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "fq_divider:u7\|clk_out " "Info: Detected ripple clock \"fq_divider:u7\|clk_out\" as buffer" {  } { { "FQ_DIVIDER.vhd" "" { Text "E:/PLDS/CLOCK/FQ_DIVIDER.vhd" 8 -1 0 } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "fq_divider:u7\|clk_out" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register alarm_counter:u4\|i_current_time\[1\]\[0\] register led_display:U8\|clock_out\[6\] 86.84 MHz 11.515 ns Internal " "Info: Clock \"clk\" has Internal fmax of 86.84 MHz between source register \"alarm_counter:u4\|i_current_time\[1\]\[0\]\" and destination register \"led_display:U8\|clock_out\[6\]\" (period= 11.515 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.810 ns + Longest register register " "Info: + Longest register to register delay is 6.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm_counter:u4\|i_current_time\[1\]\[0\] 1 REG LC_X13_Y9_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y9_N6; Fanout = 5; REG Node = 'alarm_counter:u4\|i_current_time\[1\]\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { alarm_counter:u4|i_current_time[1][0] } "NODE_NAME" } } { "ALARM_COUNTER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_COUNTER.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.114 ns) 0.656 ns display_driver:u6\|display_time\[1\]\[0\]~5014 2 COMB LC_X13_Y9_N4 1 " "Info: 2: + IC(0.542 ns) + CELL(0.114 ns) = 0.656 ns; Loc. = LC_X13_Y9_N4; Fanout = 1; COMB Node = 'display_driver:u6\|display_time\[1\]\[0\]~5014'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.656 ns" { alarm_counter:u4|i_current_time[1][0] display_driver:u6|display_time[1][0]~5014 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.540 ns) + CELL(0.114 ns) 2.310 ns display_driver:u6\|display_time\[1\]\[0\]~5015 3 COMB LC_X11_Y8_N9 7 " "Info: 3: + IC(1.540 ns) + CELL(0.114 ns) = 2.310 ns; Loc. = LC_X11_Y8_N9; Fanout = 7; COMB Node = 'display_driver:u6\|display_time\[1\]\[0\]~5015'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.654 ns" { display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.315 ns) + CELL(0.114 ns) 3.739 ns display_driver:u6\|Mux7~32 4 COMB LC_X12_Y9_N4 1 " "Info: 4: + IC(1.315 ns) + CELL(0.114 ns) = 3.739 ns; Loc. = LC_X12_Y9_N4; Fanout = 1; COMB Node = 'display_driver:u6\|Mux7~32'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.429 ns" { display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 } "NODE_NAME" } } { "DISPLAY_DRIVER.vhd" "" { Text "E:/PLDS/CLOCK/DISPLAY_DRIVER.vhd" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.114 ns) 5.079 ns led_display:U8\|Mux0~317 5 COMB LC_X12_Y8_N4 1 " "Info: 5: + IC(1.226 ns) + CELL(0.114 ns) = 5.079 ns; Loc. = LC_X12_Y8_N4; Fanout = 1; COMB Node = 'led_display:U8\|Mux0~317'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.340 ns" { display_driver:u6|Mux7~32 led_display:U8|Mux0~317 } "NODE_NAME" } } { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.253 ns) + CELL(0.478 ns) 6.810 ns led_display:U8\|clock_out\[6\] 6 REG LC_X11_Y9_N3 1 " "Info: 6: + IC(1.253 ns) + CELL(0.478 ns) = 6.810 ns; Loc. = LC_X11_Y9_N3; Fanout = 1; REG Node = 'led_display:U8\|clock_out\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.731 ns" { led_display:U8|Mux0~317 led_display:U8|clock_out[6] } "NODE_NAME" } } { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.934 ns ( 13.72 % ) " "Info: Total cell delay = 0.934 ns ( 13.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.876 ns ( 86.28 % ) " "Info: Total interconnect delay = 5.876 ns ( 86.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.810 ns" { alarm_counter:u4|i_current_time[1][0] display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.810 ns" { alarm_counter:u4|i_current_time[1][0] display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } { 0.000ns 0.542ns 1.540ns 1.315ns 1.226ns 1.253ns } { 0.000ns 0.114ns 0.114ns 0.114ns 0.114ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.444 ns - Smallest " "Info: - Smallest clock skew is -4.444 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.686 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_3 90 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 90; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.506 ns) + CELL(0.711 ns) 7.686 ns led_display:U8\|clock_out\[6\] 2 REG LC_X11_Y9_N3 1 " "Info: 2: + IC(5.506 ns) + CELL(0.711 ns) = 7.686 ns; Loc. = LC_X11_Y9_N3; Fanout = 1; REG Node = 'led_display:U8\|clock_out\[6\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.217 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.36 % ) " "Info: Total cell delay = 2.180 ns ( 28.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.506 ns ( 71.64 % ) " "Info: Total interconnect delay = 5.506 ns ( 71.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.130 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_3 90 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 90; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.527 ns) + CELL(0.935 ns) 7.931 ns fq_divider:u7\|clk_out 2 REG LC_X8_Y10_N4 25 " "Info: 2: + IC(5.527 ns) + CELL(0.935 ns) = 7.931 ns; Loc. = LC_X8_Y10_N4; Fanout = 25; REG Node = 'fq_divider:u7\|clk_out'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.462 ns" { clk fq_divider:u7|clk_out } "NODE_NAME" } } { "FQ_DIVIDER.vhd" "" { Text "E:/PLDS/CLOCK/FQ_DIVIDER.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.488 ns) + CELL(0.711 ns) 12.130 ns alarm_counter:u4\|i_current_time\[1\]\[0\] 3 REG LC_X13_Y9_N6 5 " "Info: 3: + IC(3.488 ns) + CELL(0.711 ns) = 12.130 ns; Loc. = LC_X13_Y9_N6; Fanout = 5; REG Node = 'alarm_counter:u4\|i_current_time\[1\]\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.199 ns" { fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } "NODE_NAME" } } { "ALARM_COUNTER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_COUNTER.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 25.68 % ) " "Info: Total cell delay = 3.115 ns ( 25.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.015 ns ( 74.32 % ) " "Info: Total interconnect delay = 9.015 ns ( 74.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.130 ns" { clk fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.130 ns" { clk clk~out0 fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } { 0.000ns 0.000ns 5.527ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.130 ns" { clk fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.130 ns" { clk clk~out0 fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } { 0.000ns 0.000ns 5.527ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ALARM_COUNTER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_COUNTER.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "led_display.vhd" "" { Text "E:/PLDS/CLOCK/led_display.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.810 ns" { alarm_counter:u4|i_current_time[1][0] display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.810 ns" { alarm_counter:u4|i_current_time[1][0] display_driver:u6|display_time[1][0]~5014 display_driver:u6|display_time[1][0]~5015 display_driver:u6|Mux7~32 led_display:U8|Mux0~317 led_display:U8|clock_out[6] } { 0.000ns 0.542ns 1.540ns 1.315ns 1.226ns 1.253ns } { 0.000ns 0.114ns 0.114ns 0.114ns 0.114ns 0.478ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk led_display:U8|clock_out[6] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 led_display:U8|clock_out[6] } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.130 ns" { clk fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.130 ns" { clk clk~out0 fq_divider:u7|clk_out alarm_counter:u4|i_current_time[1][0] } { 0.000ns 0.000ns 5.527ns 3.488ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}