prev_cmp_alarm_clock.tan.qmsg

来自「可以调整时间和设置闹钟的数字钟(VHDL)」· QMSG 代码 · 共 12 行 · 第 1/4 页

{ "Info" "ITDB_TH_RESULT" "alarm_controller:u3\|curr_state.s2 key_down clk 0.126 ns register " "Info: th for register \"alarm_controller:u3\|curr_state.s2\" (data pin = \"key_down\", clock pin = \"clk\") is 0.126 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.686 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_3 90 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_3; Fanout = 90; CLK Node = 'clk'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.506 ns) + CELL(0.711 ns) 7.686 ns alarm_controller:u3\|curr_state.s2 2 REG LC_X8_Y7_N3 3 " "Info: 2: + IC(5.506 ns) + CELL(0.711 ns) = 7.686 ns; Loc. = LC_X8_Y7_N3; Fanout = 3; REG Node = 'alarm_controller:u3\|curr_state.s2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.217 ns" { clk alarm_controller:u3|curr_state.s2 } "NODE_NAME" } } { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 28.36 % ) " "Info: Total cell delay = 2.180 ns ( 28.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.506 ns ( 71.64 % ) " "Info: Total interconnect delay = 5.506 ns ( 71.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk alarm_controller:u3|curr_state.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 alarm_controller:u3|curr_state.s2 } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.575 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.575 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_down 1 CLK PIN_48 33 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_48; Fanout = 33; CLK Node = 'key_down'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { key_down } "NODE_NAME" } } { "ALARM_CLOCK.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CLOCK.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.797 ns) + CELL(0.309 ns) 7.575 ns alarm_controller:u3\|curr_state.s2 2 REG LC_X8_Y7_N3 3 " "Info: 2: + IC(5.797 ns) + CELL(0.309 ns) = 7.575 ns; Loc. = LC_X8_Y7_N3; Fanout = 3; REG Node = 'alarm_controller:u3\|curr_state.s2'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.106 ns" { key_down alarm_controller:u3|curr_state.s2 } "NODE_NAME" } } { "ALARM_CONTROLLER.vhd" "" { Text "E:/PLDS/CLOCK/ALARM_CONTROLLER.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns ( 23.47 % ) " "Info: Total cell delay = 1.778 ns ( 23.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.797 ns ( 76.53 % ) " "Info: Total interconnect delay = 5.797 ns ( 76.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.575 ns" { key_down alarm_controller:u3|curr_state.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.575 ns" { key_down key_down~out0 alarm_controller:u3|curr_state.s2 } { 0.000ns 0.000ns 5.797ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.686 ns" { clk alarm_controller:u3|curr_state.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.686 ns" { clk clk~out0 alarm_controller:u3|curr_state.s2 } { 0.000ns 0.000ns 5.506ns } { 0.000ns 1.469ns 0.711ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.575 ns" { key_down alarm_controller:u3|curr_state.s2 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.575 ns" { key_down key_down~out0 alarm_controller:u3|curr_state.s2 } { 0.000ns 0.000ns 5.797ns } { 0.000ns 1.469ns 0.309ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "109 " "Info: Allocated 109 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue May 13 23:40:04 2008 " "Info: Processing ended: Tue May 13 23:40:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}