alarm_clock.vhd.bak

可以调整时间和设置闹钟的数字钟(VHDL)

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
use ieee.std_logic_unsigned.all;

entity alarm_clock is
	port(keypad: in std_logic_vector(9 downto 0);
		key_down: in std_logic;
		alarm_button: in std_logic;
		time_button: in std_logic;
		clk: in std_logic;
		reset: in std_logic;
		displayseg: out std_logic_vector(6 downto 0);
		--display: out t_display;
		sound_alarm: out std_logic);
end alarm_clock;

architecture art of alarm_clock is
	component decoder is
		port(keypad: in std_logic_vector(9 downto 0);
			value: out t_digital);
	end component decoder;
	
	component key_buffer is
		port(key: in t_digital;
		clk: in std_logic;
		reset: in std_logic;
		new_time: out t_clock_time);
    end component key_buffer;

	component alarm_controller is
		port(	key: in std_logic;
			alarm_button:	in std_logic;
			time_button :	in std_logic;
			clk			:	in std_logic;
			reset		:	in std_logic;
			load_new_a	:	out std_logic;
			load_new_c	:	out std_logic;
			show_new_time:  out std_logic;
			show_a		:	out std_logic);
	end component alarm_controller;
	
	component alarm_counter is
		port(new_current_time: in t_clock_time;
		load_new_c: in std_logic;
		clk: in std_logic;
		reset : in std_logic;
		current_time: out t_clock_time);
	end component alarm_counter;
	
	component alarm_reg is
		port(new_alarm_time: in t_clock_time;
		load_new_a: in std_logic;
		clk: in std_logic;
		reset: in std_logic;
		alarm_time: out t_clock_time);
	end component alarm_reg;
	
	component display_driver is
		port(alarm_time: in t_clock_time;
		current_time: in t_clock_time;
		new_time: in t_clock_time;
		show_new_time: in std_logic;
		show_a: in std_logic;
		sound_alarm: out std_logic;
		display: out t_display);
	end component display_driver;
	
	component fq_divider is
		port(clk_in : in std_logic;
		reset: in std_logic;
		clk_out: out std_logic);
	end component fq_divider;
	
	component led_display is
		port (	displayseg  : t_display;
			     clk		: in std_logic;
			    clock_out   : out std_logic_vector (6 downto 0));
	end component led_display;
	
	signal display: t_display;
	signal s0: t_digital;
	signal s1,s2,s3,s4,s5: std_logic;
	signal s6,s7,s8:t_clock_time;
	begin
		u1: decoder port map(keypad,s0);
		u2: key_buffer port map(s0,key_down,reset,s6);
		u3: alarm_controller port map( key_down,alarm_button,time_button,clk,reset,s1,s2,s3,s4);
		u4: alarm_counter port map(s6,s2,s5,reset,s8);
		u5: alarm_reg port map(s6,s1,clk,reset,s7);
		u6: display_driver port map(s7,s6,s8,s3,s4,sound_alarm,display);
		u7: fq_divider port map(clk,reset,s5);
		U8: led_display port map(display,clk,displayseg);
end architecture art;