alarm_reg.vhd

来自「可以调整时间和设置闹钟的数字钟(VHDL)」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity alarm_reg is
	port(new_alarm_time: in t_clock_time;
		load_new_a: in std_logic;
		clk: in std_logic;
		reset: in std_logic;
		alarm_time: out t_clock_time);
end alarm_reg;

architecture art of alarm_reg  is
	begin
		process(clk,reset,load_new_a) is
			begin
				if(reset='1') then
					alarm_time<=(0,0,0,0,0,0);
				else
					if(rising_edge(clk)) then
						if(load_new_a='1') then
							alarm_time<=new_alarm_time;
						elsif(load_new_a/='0') then
							assert false 
							report "uncertain load_new_alarm control!"
							severity warning;
						end if;
					end if;
				end if;
		end process;
end art;