alarm_counter.vhd.bak

可以调整时间和设置闹钟的数字钟(VHDL)

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity alarm_counter is
	port(new_current_time: in t_clock_time;
		load_new_c: in std_logic;
		clk: in std_logic;
		reset : in std_logic;
		current_time: out t_clock_time);
end alarm_counter;

architecture art of alarm_counter is
	signal i_current_time: t_clock_time;
	begin
		process(clk,reset,load_new_c,new_current_time) is
			variable c_t: t_clock_time;
			begin
			if(reset='1') then
				i_current_time<=(0,0,0,0,0,0);
			elsif(load_new_c='1') then
				i_current_time<=new_current_time;
			elsif rising_edge(clk) then
				c_t:=i_current_time;
				if(c_t(0)<9) then
					c_t(0):=c_t(0) +1;
				else 
					c_t(0):=0;
					if(c_t(1)<5) then
						c_t(1):=c_t(1)+1;
					else 
						c_t(1):=0;
						if(c_t(2)<9) then 
							c_t(2) :=c_t(2)+1;
							else 
								c_t(2):=0;
								if(c_t(3)<5) then
									c_t(3):=c_t(3)+1;
								else 
									c_t(3):=0;
									if(c_t(5)<2) then
										if(c_t(4)<9) then
											c_t(4):=c_t(4)+1;
										else
											c_t(5):=c_t(5)+1;
											c_t(4):=0;
										end if;
									else 
										if(c_t(4)<3) then
											c_t(4):=c_t(4)+1;
										else
											c_t(4):=0;
											c_t(5):=0;
										end if;
									end if;
							end if;
					end if;
						i_current_time<=c_t;
					end if;
			end process;
			current_time<=i_current_time;
end art;