fq_divider.vhd

来自「可以调整时间和设置闹钟的数字钟(VHDL)」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;

entity fq_divider is
	port(clk_in : in std_logic;
		reset: in std_logic;
		clk_out: out std_logic);
end fq_divider;

architecture art of fq_divider is
	constant divide_period: t_short:=600;
	begin
		divide_clk: process(reset,clk_in) is
				variable cnt: t_short;
				begin
					if(reset='1') then
						cnt:=0;
						clk_out<='0';
					elsif(rising_edge(clk_in)) then
						if(cnt<(divide_period/2)) then
							clk_out<='1';
							cnt:=cnt+1;
						elsif(cnt<(divide_period-1)) then
								clk_out<='0';
								cnt:=cnt+1;
							else 
								cnt:=0;
						end if;
					end if;
			end process divide_clk;
end art;