📄 alarm_controller.vhd
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library ieee;
use ieee.std_logic_1164.all;
use work.p_alarm.all;
entity alarm_controller is
port( key: in std_logic;
alarm_button: in std_logic;
time_button : in std_logic;
clk : in std_logic;
reset : in std_logic;
load_new_a : out std_logic;
load_new_c : out std_logic;
show_new_time: out std_logic;
show_a : out std_logic);
end alarm_controller;
architecture art of alarm_controller is
type t_state is(s0,s1,s2,s3,s4);
constant key_timeout : t_short:=500;
constant show_alarm_timeout: t_short:=500;
signal curr_state: t_state;
signal next_state: t_state;
signal counter_k: t_short;
signal enable_count_k: std_logic;
signal count_k_end: std_logic;
signal counter_a: t_short;
signal enable_count_a: std_logic;
signal count_a_end: std_logic;
begin
states: process(clk,reset) is
begin
if(reset='1') then
curr_state<=s0;
elsif(rising_edge(clk)) then
curr_state<=next_state;
end if;
end process;
ariths: process(key,alarm_button,time_button,curr_state,count_a_end,count_k_end) is
begin
next_state<=curr_state;
load_new_a<='0';
load_new_c<='0';
show_a<='0';
show_new_time<='0';
enable_count_k<='0';
enable_count_a<='0';
case curr_state is
when s0=>
if(key='1') then
next_state<=s1;
show_new_time<='1';
elsif(alarm_button='1') then
next_state<=s4;
show_a<='1';
else
next_state<=s0;
end if;
when s1=>
if(key='1') then
next_state<=s1;
elsif(alarm_button='1') then
next_state<=s2;
load_new_a<='1';
elsif(time_button='1') then
next_state<=s3;
load_new_c<='1';
else
if(count_k_end='1') then
next_state<=s0;
else
next_state<=s1;
end if;
enable_count_k<='1';
end if;
show_new_time<='1';
when s2=>
if(alarm_button='1') then
next_state<=s2;
load_new_a<='1';
else
next_state<=s0;
end if;
when s3=>
if(time_button='1') then
next_state<=s3;
load_new_c<='1';
else
next_state<=s0;
end if;
when s4=>
if(key='1') then
next_state<=s1;
else
next_state<=s4;
if(count_a_end='1') then
next_state<=s0;
else
next_state<=s4;
show_a<='1';
end if;
enable_count_a<='1';
end if;
when others=>
null;
end case;
end process;
count_key: process(enable_count_k,clk) is
begin
if(enable_count_k='0') then
counter_k<=0;
count_k_end<='0';
elsif(rising_edge(clk)) then
if(counter_k>=key_timeout) then
count_k_end<='1';
else
counter_k<=counter_k+1;
end if;
end if;
end process;
count_alarm: process (enable_count_a,clk) is
begin
if(enable_count_a='0') then
counter_a<=0;
count_a_end<='0';
elsif(rising_edge(clk)) then
if(counter_a>=show_alarm_timeout) then
count_a_end<='1';
else
counter_a<=counter_a+1;
end if;
end if;
end process;
end art;
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