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📄 spi_master.fit.rpt

📁 AN485_CH-MAX II CPLD 中的串行外设接口主机(verilog SPI)
💻 RPT
📖 第 1 页 / 共 5 页
字号:
; 9                                           ; 1                            ;
; 10                                          ; 2                            ;
; 11                                          ; 0                            ;
; 12                                          ; 0                            ;
; 13                                          ; 0                            ;
; 14                                          ; 1                            ;
; 15                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Passive Serial      ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+--------------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                            ;
+--------------------------------------------------------------------------------+-----------------+
; Name                                                                           ; Value           ;
+--------------------------------------------------------------------------------+-----------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff              ;
; Mid Wire Use - Fit Attempt 1                                                   ; 19              ;
; Mid Slack - Fit Attempt 1                                                      ; -15414          ;
; Internal Atom Count - Fit Attempt 1                                            ; 68              ;
; LE/ALM Count - Fit Attempt 1                                                   ; 68              ;
; LAB Count - Fit Attempt 1                                                      ; 11              ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.091           ;
; Inputs per LAB - Fit Attempt 1                                                 ; 7.182           ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.364           ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:7;1:4         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:3;1:8         ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:2;1:5;2:4     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:2;1:6;2:3     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2;1:4;2:5     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2;1:5;2:4     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:10;1:1        ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:11            ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:2;1:6;2:3     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2;1:4;2:4;3:1 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:3;2:7     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:8;1:3         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:6;2:4     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:6;1:5         ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:5;1:6         ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:11            ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:11            ;
; LEs in Chains - Fit Attempt 1                                                  ; 7               ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0               ;
; LABs with Chains - Fit Attempt 1                                               ; 1               ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0               ;
; Time - Fit Attempt 1                                                           ; 0               ;
+--------------------------------------------------------------------------------+-----------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 5      ;
; Early Slack - Fit Attempt 1         ; -13745 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 9      ;
; Mid Slack - Fit Attempt 1           ; -14134 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 10     ;
; Late Slack - Fit Attempt 1          ; -14134 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.032  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -11869 ;
; Early Wire Use - Fit Attempt 1      ; 10     ;
; Peak Regional Wire - Fit Attempt 1  ; 9      ;
; Mid Slack - Fit Attempt 1           ; -13501 ;
; Late Slack - Fit Attempt 1          ; -13501 ;
; Late Wire Use - Fit Attempt 1       ; 11     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.109  ;
+-------------------------------------+--------+


+----------------------------------------------------------------+
; Fitter INI Usage                                               ;
+----------------------+-----------------------------------------+
; Option               ; Usage                                   ;
+----------------------+-----------------------------------------+
; Initialization file: ; c:/altera/72_cc/quartus/bin/quartus.ini ;
; debug_msg            ; OFF                                     ;
+----------------------+-----------------------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 16:41:56 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SPI_Master -c SPI_Master
Info: Selected device EPM240GT100C3 for design "SPI_Master"
Warning: The high junction temperature operating condition is not set. Assuming a default value of '85'.
Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570GT100C3 is compatible
Warning: No exact pin location assignment(s) for 25 pins of 25 total pins
    Info: Pin mosi not assigned to an exact location on the device
    Info: Pin sclk not assigned to an exact location on the device
    Info: Pin ss[0] not assigned to an exact location on the device
    Info: Pin ss[1] not assigned to an exact location on the device
    Info: Pin ss[2] not assigned to an exact location on the device
    Info: Pin ss[3] not assigned to an exact location on 

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