spi_master.tan.qmsg

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

{ "Info" "ITDB_FULL_TPD_RESULT" "RD data_bus\[3\] 2.987 ns Longest " "Info: Longest tpd from source pin \"RD\" to destination pin \"data_bus\[3\]\" is 2.987 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns RD 1 PIN PIN_20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_20; Fanout = 9; PIN Node = 'RD'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { RD } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.276 ns) + CELL(1.003 ns) 2.987 ns data_bus\[3\] 2 PIN PIN_6 0 " "Info: 2: + IC(1.276 ns) + CELL(1.003 ns) = 2.987 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'data_bus\[3\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.279 ns" { RD data_bus[3] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.711 ns ( 57.28 % ) " "Info: Total cell delay = 1.711 ns ( 57.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.276 ns ( 42.72 % ) " "Info: Total interconnect delay = 1.276 ns ( 42.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.987 ns" { RD data_bus[3] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.987 ns" { RD {} RD~combout {} data_bus[3] {} } { 0.000ns 0.000ns 1.276ns } { 0.000ns 0.708ns 1.003ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "shift_register\[0\] miso pro_clk 8.176 ns register " "Info: th for register \"shift_register\[0\]\" (data pin = \"miso\", clock pin = \"pro_clk\") is 8.176 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk destination 11.763 ns + Longest register " "Info: + Longest clock path from clock \"pro_clk\" to destination register is 11.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.809 ns) 2.328 ns control\[1\] 2 REG LC_X3_Y2_N9 4 " "Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X3_Y2_N9; Fanout = 4; REG Node = 'control\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { pro_clk control[1] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.571 ns) 4.137 ns Mux0~53 3 COMB LC_X3_Y2_N8 1 " "Info: 3: + IC(1.238 ns) + CELL(0.571 ns) = 4.137 ns; Loc. = LC_X3_Y2_N8; Fanout = 1; COMB Node = 'Mux0~53'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { control[1] Mux0~53 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.191 ns) + CELL(0.125 ns) 4.453 ns Mux0~54 4 COMB LC_X3_Y2_N9 1 " "Info: 4: + IC(0.191 ns) + CELL(0.125 ns) = 4.453 ns; Loc. = LC_X3_Y2_N9; Fanout = 1; COMB Node = 'Mux0~54'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.316 ns" { Mux0~53 Mux0~54 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.462 ns) 6.017 ns Mux0 5 COMB LC_X4_Y2_N2 1 " "Info: 5: + IC(1.102 ns) + CELL(0.462 ns) = 6.017 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Mux0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { Mux0~54 Mux0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.809 ns) 7.904 ns sclk~reg0 6 REG LC_X4_Y3_N2 8 " "Info: 6: + IC(1.078 ns) + CELL(0.809 ns) = 7.904 ns; Loc. = LC_X4_Y3_N2; Fanout = 8; REG Node = 'sclk~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.887 ns" { Mux0 sclk~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.462 ns) 9.187 ns always2~1 7 COMB LC_X3_Y3_N3 9 " "Info: 7: + IC(0.821 ns) + CELL(0.462 ns) = 9.187 ns; Loc. = LC_X3_Y3_N3; Fanout = 9; COMB Node = 'always2~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { sclk~reg0 always2~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.574 ns) 11.763 ns s