spi_master.tan.qmsg

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "21 " "Warning: Found 21 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux0~55 " "Info: Detected gated clock \"Mux0~55\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~55" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "control\[0\] " "Info: Detected ripple clock \"control\[0\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "control\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "control\[1\] " "Info: Detected ripple clock \"control\[1\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "control\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~53 " "Info: Detected gated clock \"Mux0~53\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~53" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "control\[2\] " "Info: Detected ripple clock \"control\[2\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "control\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~56 " "Info: Detected gated clock \"Mux0~56\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~56" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~54 " "Info: Detected gated clock \"Mux0~54\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~54" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[7\] " "Info: Detected ripple clock \"clk_divide\[7\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[6\] " "Info: Detected ripple clock \"clk_divide\[6\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[5\] " "Info: Detected ripple clock \"clk_divide\[5\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[4\] " "Info: Detected ripple clock \"clk_divide\[4\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[3\] " "Info: Detected ripple clock \"clk_divide\[3\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[2\] " "Info: Detected ripple clock \"clk_divide\[2\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[1\] " "Info: Detected ripple clock \"clk_divide\[1\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_divide\[0\] " "Info: Detected ripple clock \"clk_divide\[0\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 57 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_divide\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "control\[4\] " "Info: Detected ripple clock \"control\[4\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "control\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0 " "Info: Detected gated clock \"Mux0\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "slave_cs " "Info: Detected ripple clock \"slave_cs\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 30 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "slave_cs" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "control\[3\] " "Info: Detected ripple clock \"control\[3\]\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 24 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "control\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sclk~reg0 " "Info: Detected ripple clock \"sclk~reg0\" as buffer" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "sclk~reg0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "always2~1 " "Info: Detected gated clock \"always2~1\" as buffer" {  } { { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "always2~1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "pro_clk register shift_register\[7\] register rxdata\[7\] 58.71 MHz 17.032 ns Internal " "Info: Clock \"pro_clk\" has Internal fmax of 58.71 MHz between source register \"shift_register\[7\]\" and destination register \"rxdata\[7\]\" (period= 17.032 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.928 ns + Longest register register " "Info: + Longest register to register delay is 0.928 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_register\[7\] 1 REG LC_X3_Y4_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; REG Node = 'shift_register\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_register[7] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.559 ns) + CELL(0.369 ns) 0.928 ns rxdata\[7\] 2 REG LC_X3_Y4_N9 1 " "Info: 2: + IC(0.559 ns) + CELL(0.369 ns) = 0.928 ns; Loc. = LC_X3_Y4_N9; Fanout = 1; REG Node = 'rxdata\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.928 ns" { shift_register[7] rxdata[7] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.369 ns ( 39.76 % ) " "Info: Total cell delay = 0.369 ns ( 39.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.559 ns ( 60.24 % ) " "Info: Total interconnect delay = 0.559 ns ( 60.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.928 ns" { shift_register[7] rxdata[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "0.928 ns" { shift_register[7] {} rxdata[7] {} } { 0.000ns 0.559ns } { 0.000ns 0.369ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.145 ns - Smallest " "Info: - Smallest clock skew is -7.145 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk destination 4.618 ns + Shortest register " "Info: + Shortest clock path from clock \"pro_clk\" to destination register is 4.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.809 ns) 2.328 ns slave_cs 2 REG LC_X2_Y3_N7 23 " "Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X2_Y3_N7; Fanout = 23; REG Node = 'slave_cs'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { pro_clk slave_cs } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.716 ns) + CELL(0.574 ns) 4.618 ns rxdata\[7\] 3 REG LC_X3_Y4_N9 1 " "Info: 3: + IC(1.716 ns) + CELL(0.574 ns) = 4.618 ns; Loc. = LC_X3_Y4_N9; Fanout = 1; REG Node = 'rxdata\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.290 ns" { slave_cs rxdata[7] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.110 ns ( 45.69 % ) " "Info: Total cell delay = 2.110 ns ( 45.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.508 ns ( 54.31 % ) " "Info: Total interconnect delay = 2.508 ns ( 54.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.618 ns" { pro_clk slave_cs rxdata[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.618 ns" { pro_clk {} pro_clk~combout {} slave_cs {} rxdata[7] {} } { 0.000ns 0.000ns 0.792ns 1.716ns } { 0.000ns 0.727ns 0.809ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk source 11.763 ns - Longest register " "Info: - Longest clock path from clock \"pro_clk\" to source register is 11.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.809 ns) 2.328 ns control\[1\] 2 REG LC_X3_Y2_N9 4 " "Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X3_Y2_N9; Fanout = 4; REG Node = 'control\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { pro_clk control[1] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.571 ns) 4.137 ns Mux0~53 3 COMB LC_X3_Y2_N8 1 " "Info: 3: + IC(1.238 ns) + CELL(0.571 ns) = 4.137 ns; Loc. = LC_X3_Y2_N8; Fanout = 1; COMB Node = 'Mux0~53'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { control[1] Mux0~53 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.191 ns) + CELL(0.125 ns) 4.453 ns Mux0~54 4 COMB LC_X3_Y2_N9 1 " "Info: 4: + IC(0.191 ns) + CELL(0.125 ns) = 4.453 ns; Loc. = LC_X3_Y2_N9; Fanout = 1; COMB Node = 'Mux0~54'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.316 ns" { Mux0~53 Mux0~54 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.462 ns) 6.017 ns Mux0 5 COMB LC_X4_Y2_N2 1 " "Info: 5: + IC(1.102 ns) + CELL(0.462 ns) = 6.017 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Mux0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { Mux0~54 Mux0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.809 ns) 7.904 ns sclk~reg0 6 REG LC_X4_Y3_N2 8 " "Info: 6: + IC(1.078 ns) + CELL(0.809 ns) = 7.904 ns; Loc. = LC_X4_Y3_N2; Fanout = 8; REG Node = 'sclk~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.887 ns" { Mux0 sclk~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.462 ns) 9.187 ns always2~1 7 COMB LC_X3_Y3_N3 9 " "Info: 7: + IC(0.821 ns) + CELL(0.462 ns) = 9.187 ns; Loc. = LC_X3_Y3_N3; Fanout = 9; COMB Node = 'always2~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { sclk~reg0 always2~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.574 ns) 11.763 ns shift_register\[7\] 8 REG LC_X3_Y4_N8 2 " "Info: 8: + IC(2.002 ns) + CELL(0.574 ns) = 11.763 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; REG Node = 'shift_register\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { always2~1 shift_register[7] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.539 ns ( 38.59 % ) " "Info: Total cell delay = 4.539 ns ( 38.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.224 ns ( 61.41 % ) " "Info: Total interconnect delay = 7.224 ns ( 61.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 shift_register[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} shift_register[7] {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.618 ns" { pro_clk slave_cs rxdata[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.618 ns" { pro_clk {} pro_clk~combout {} slave_cs {} rxdata[7] {} } { 0.000ns 0.000ns 0.792ns 1.716ns } { 0.000ns 0.727ns 0.809ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 shift_register[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} shift_register[7] {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 87 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 87 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.928 ns" { shift_register[7] rxdata[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "0.928 ns" { shift_register[7] {} rxdata[7] {} } { 0.000ns 0.559ns } { 0.000ns 0.369ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.618 ns" { pro_clk slave_cs rxdata[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.618 ns" { pro_clk {} pro_clk~combout {} slave_cs {} rxdata[7] {} } { 0.000ns 0.000ns 0.792ns 1.716ns } { 0.000ns 0.727ns 0.809ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 shift_register[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} shift_register[7] {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "pro_clk 21 " "Warning: Circuit may not operate. Detected 21 non-operational path(s) clocked by clock \"pro_clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}