spi_master.hier_info

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

|SPI_Master
miso => shift_register[0].DATAIN
mosi <= mosi~reg0.DB_MAX_OUTPUT_PORT_TYPE
sclk <= sclk~reg0.DB_MAX_OUTPUT_PORT_TYPE
ss[0] <= ss~19.DB_MAX_OUTPUT_PORT_TYPE
ss[1] <= ss~17.DB_MAX_OUTPUT_PORT_TYPE
ss[2] <= ss~14.DB_MAX_OUTPUT_PORT_TYPE
ss[3] <= ss~12.DB_MAX_OUTPUT_PORT_TYPE
ss[4] <= ss~9.DB_MAX_OUTPUT_PORT_TYPE
ss[5] <= ss~7.DB_MAX_OUTPUT_PORT_TYPE
ss[6] <= ss~4.DB_MAX_OUTPUT_PORT_TYPE
ss[7] <= ss~2.DB_MAX_OUTPUT_PORT_TYPE
data_bus[0] <= data_bus~15
data_bus[1] <= data_bus~14
data_bus[2] <= data_bus~13
data_bus[3] <= data_bus~12
data_bus[4] <= data_bus~11
data_bus[5] <= data_bus~10
data_bus[6] <= data_bus~9
data_bus[7] <= data_bus~8
CS => always5~0.IN0
CS => control[0].ENA
CS => control[1].ENA
CS => control[2].ENA
CS => control[3].ENA
CS => control[4].ENA
CS => control[5].ENA
CS => control[6].ENA
CS => control[7].ENA
CS => txdata[0].ENA
CS => txdata[1].ENA
CS => txdata[2].ENA
CS => txdata[3].ENA
CS => txdata[4].ENA
CS => txdata[5].ENA
CS => txdata[6].ENA
CS => txdata[7].ENA
CS => data_out[0].ENA
CS => data_out[1].ENA
CS => data_out[2].ENA
CS => data_out[3].ENA
CS => data_out[4].ENA
CS => data_out[5].ENA
CS => data_out[6].ENA
CS => data_out[7].ENA
addr[0] => Decoder0.IN1
addr[0] => Mux8.IN3
addr[0] => Mux7.IN3
addr[0] => Mux6.IN3
addr[0] => Mux5.IN3
addr[0] => Mux4.IN3
addr[0] => Mux3.IN3
addr[0] => Mux2.IN3
addr[0] => Mux1.IN3
addr[0] => always5~2.IN1
addr[1] => Decoder0.IN0
addr[1] => Mux8.IN2
addr[1] => Mux7.IN2
addr[1] => Mux6.IN2
addr[1] => Mux5.IN2
addr[1] => Mux4.IN2
addr[1] => Mux3.IN2
addr[1] => Mux2.IN2
addr[1] => Mux1.IN2
addr[1] => always5~1.IN1
pro_clk => slave_cs.CLK
pro_clk => spi_word_send.CLK
pro_clk => data_out[7].CLK
pro_clk => data_out[6].CLK
pro_clk => data_out[5].CLK
pro_clk => data_out[4].CLK
pro_clk => data_out[3].CLK
pro_clk => data_out[2].CLK
pro_clk => data_out[1].CLK
pro_clk => data_out[0].CLK
pro_clk => txdata[7].CLK
pro_clk => txdata[6].CLK
pro_clk => txdata[5].CLK
pro_clk => txdata[4].CLK
pro_clk => txdata[3].CLK
pro_clk => txdata[2].CLK
pro_clk => txdata[1].CLK
pro_clk => txdata[0].CLK
pro_clk => control[7].CLK
pro_clk => control[6].CLK
pro_clk => control[5].CLK
pro_clk => control[4].CLK
pro_clk => control[3].CLK
pro_clk => control[2].CLK
pro_clk => control[1].CLK
pro_clk => control[0].CLK
pro_clk => clk_divide[7].CLK
pro_clk => clk_divide[6].CLK
pro_clk => clk_divide[5].CLK
pro_clk => clk_divide[4].CLK
pro_clk => clk_divide[3].CLK
pro_clk => clk_divide[2].CLK
pro_clk => clk_divide[1].CLK
pro_clk => clk_divide[0].CLK
WR => txdata~7.OUTPUTSELECT
WR => txdata~6.OUTPUTSELECT
WR => txdata~5.OUTPUTSELECT
WR => txdata~4.OUTPUTSELECT
WR => txdata~3.OUTPUTSELECT
WR => txdata~2.OUTPUTSELECT
WR => txdata~1.OUTPUTSELECT
WR => txdata~0.OUTPUTSELECT
WR => control~7.OUTPUTSELECT
WR => control~6.OUTPUTSELECT
WR => control~5.OUTPUTSELECT
WR => control~4.OUTPUTSELECT
WR => control~3.OUTPUTSELECT
WR => control~2.OUTPUTSELECT
WR => control~1.OUTPUTSELECT
WR => control~0.OUTPUTSELECT
WR => always5~0.IN1
RD => data_out_en[7].OE
RD => data_out_en[6].OE
RD => data_out_en[5].OE
RD => data_out_en[4].OE
RD => data_out_en[3].OE
RD => data_out_en[2].OE
RD => data_out_en[1].OE
RD => data_out_en[0].OE
RD => data_out~15.OUTPUTSELECT
RD => data_out~14.OUTPUTSELECT
RD => data_out~13.OUTPUTSELECT
RD => data_out~12.OUTPUTSELECT
RD => data_out~11.OUTPUTSELECT
RD => data_out~10.OUTPUTSELECT
RD => data_out~9.OUTPUTSELECT
RD => data_out~8.OUTPUTSELECT
RD => data_out~7.OUTPUTSELECT
RD => data_out~6.OUTPUTSELECT
RD => data_out~5.OUTPUTSELECT
RD => data_out~4.OUTPUTSELECT
RD => data_out~3.OUTPUTSELECT
RD => data_out~2.OUTPUTSELECT
RD => data_out~1.OUTPUTSELECT
RD => data_out~0.OUTPUTSELECT