prev_cmp_spi_master.fit.qmsg

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.811 ns register pin " "Info: Estimated most critical path is register to pin delay of 1.811 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mosi~reg0 1 REG LAB_X7_Y4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y4; Fanout = 1; REG Node = 'mosi~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { mosi~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 77 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(1.454 ns) 1.811 ns mosi 2 PIN PIN_73 0 " "Info: 2: + IC(0.357 ns) + CELL(1.454 ns) = 1.811 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'mosi'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.811 ns" { mosi~reg0 mosi } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 80.29 % ) " "Info: Total cell delay = 1.454 ns ( 80.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.357 ns ( 19.71 % ) " "Info: Total interconnect delay = 0.357 ns ( 19.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.811 ns" { mosi~reg0 mosi } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Warning" "WFITAPI_FITAPI_WARNING_VPR_VERY_HIGH_HOLD_REQUIREMENTS_DETECTED" "2 207 " "Warning: 2 (of 207) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." { { "Info" "IFITAPI_FITAPI_INFO_VPR_REGISTERS_WITH_VERY_HIGH_HOLD_REQUIREMENTS" "2 " "Info: Found 2 Registers with very high hold time requirements" { { "Info" "IFITAPI_FITAPI_ATOM_NAME" "data_out\[0\] " "Info: Node \"data_out\[0\]\"" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[0\]" } } } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_out[0] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_out[0] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_ATOM_NAME" "data_out\[1\] " "Info: Node \"data_out\[1\]\"" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } } { "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72_cc/quartus/bin/Assignment Editor.qase" 1 { { 0 "data_out\[1\]" } } } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_out[1] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_out[1] } "NODE_NAME" } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Found %1!d! Registers with very high hold time requirements" 0 0 "" 0}  } {  } 0 0 "%1!d! (of %2!d!) connections in the design require a large routing delay to achieve hold requirements. Please check the circuit's timing constraints and clocking methodology, especially multicycles and gated clocks." 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "9 " "Info: Average interconnect usage is 9% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "9 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 9% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "RD " "Info: Following pins have the same output enable: RD" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[0\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[0\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[0] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[0] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[2\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[2\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[2] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[2] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[4\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[4\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[4] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[4] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[6\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[6\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[6] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[6] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[1\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[1\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[1] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[1] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[3\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[3\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[3] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[3] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[5\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[5\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[5] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[5] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional data_bus\[7\] 3.3-V LVTTL " "Info: Type bidirectional pin data_bus\[7\] uses the 3.3-V LVTTL I/O standard" {  } { { "c:/altera/72_cc/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/72_cc/quartus/bin/pin_planner.ppl" { data_bus[7] } } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 8 -1 0 } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { data_bus[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.fit.smsg " "Info: Generated suppressed messages file D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "177 " "Info: Allocated 177 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 15 16:35:58 2007 " "Info: Processing ended: Thu Nov 15 16:35:58 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}