spi_master.fit.qmsg

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "pro_clk Global clock in PIN 14 " "Info: Automatically promoted signal \"pro_clk\" to use Global clock in PIN 14" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "always2~1 Global clock " "Info: Automatically promoted signal \"always2~1\" to use Global clock" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { always2~1 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { always2~1 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "slave_cs Global clock " "Info: Automatically promoted some destinations of signal \"slave_cs\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sclk~reg0 " "Info: Destination \"sclk~reg0\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "slave_cs " "Info: Destination \"slave_cs\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 30 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~19 " "Info: Destination \"ss~19\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~124 " "Info: Destination \"ss~124\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~125 " "Info: Destination \"ss~125\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~126 " "Info: Destination \"ss~126\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~127 " "Info: Destination \"ss~127\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~128 " "Info: Destination \"ss~128\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~129 " "Info: Destination \"ss~129\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ss~130 " "Info: Destination \"ss~130\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 30 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sclk~reg0 Global clock " "Info: Automatically promoted some destinations of signal \"sclk~reg0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sclk " "Info: Destination \"sclk\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "slave_cs~97 " "Info: Destination \"slave_cs~97\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 30 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "always2~1 " "Info: Destination \"always2~1\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sclk~reg0_wirecell " "Info: Destination \"sclk~reg0_wirecell\" may be non-global or may not use global clock" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 16 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0}  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0 "" 0}