prev_cmp_spi_master.tan.qmsg

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "shift_register\[1\] shift_register\[2\] pro_clk 5.145 ns " "Info: Found hold time violation between source  pin or register \"shift_register\[1\]\" and destination pin or register \"shift_register\[2\]\" for clock \"pro_clk\" (Hold time is 5.145 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.487 ns + Largest " "Info: + Largest clock skew is 6.487 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk destination 11.763 ns + Longest register " "Info: + Longest clock path from clock \"pro_clk\" to destination register is 11.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.809 ns) 2.328 ns control\[1\] 2 REG LC_X3_Y2_N9 4 " "Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X3_Y2_N9; Fanout = 4; REG Node = 'control\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { pro_clk control[1] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.571 ns) 4.137 ns Mux0~53 3 COMB LC_X3_Y2_N8 1 " "Info: 3: + IC(1.238 ns) + CELL(0.571 ns) = 4.137 ns; Loc. = LC_X3_Y2_N8; Fanout = 1; COMB Node = 'Mux0~53'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { control[1] Mux0~53 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.191 ns) + CELL(0.125 ns) 4.453 ns Mux0~54 4 COMB LC_X3_Y2_N9 1 " "Info: 4: + IC(0.191 ns) + CELL(0.125 ns) = 4.453 ns; Loc. = LC_X3_Y2_N9; Fanout = 1; COMB Node = 'Mux0~54'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.316 ns" { Mux0~53 Mux0~54 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.462 ns) 6.017 ns Mux0 5 COMB LC_X4_Y2_N2 1 " "Info: 5: + IC(1.102 ns) + CELL(0.462 ns) = 6.017 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Mux0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { Mux0~54 Mux0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.809 ns) 7.904 ns sclk~reg0 6 REG LC_X4_Y3_N2 8 " "Info: 6: + IC(1.078 ns) + CELL(0.809 ns) = 7.904 ns; Loc. = LC_X4_Y3_N2; Fanout = 8; REG Node = 'sclk~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.887 ns" { Mux0 sclk~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.462 ns) 9.187 ns always2~1 7 COMB LC_X3_Y3_N3 9 " "Info: 7: + IC(0.821 ns) + CELL(0.462 ns) = 9.187 ns; Loc. = LC_X3_Y3_N3; Fanout = 9; COMB Node = 'always2~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { sclk~reg0 always2~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.574 ns) 11.763 ns shift_register\[2\] 8 REG LC_X5_Y2_N5 2 " "Info: 8: + IC(2.002 ns) + CELL(0.574 ns) = 11.763 ns; Loc. = LC_X5_Y2_N5; Fanout = 2; REG Node = 'shift_register\[2\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { always2~1 shift_register[2] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.539 ns ( 38.59 % ) " "Info: Total cell delay = 4.539 ns ( 38.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.224 ns ( 61.41 % ) " "Info: Total interconnect delay = 7.224 ns ( 61.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 shift_register[2] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} shift_register[2] {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk source 5.276 ns - Shortest register " "Info: - Shortest clock path from clock \"pro_clk\" to source register is 5.276 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.809 ns) 2.328 ns control\[4\] 2 REG LC_X3_Y3_N3 1 " "Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X3_Y3_N3; Fanout = 1; REG Node = 'control\[4\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { pro_clk control[4] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.372 ns) 2.700 ns always2~1 3 COMB LC_X3_Y3_N3 9 " "Info: 3: + IC(0.000 ns) + CELL(0.372 ns) = 2.700 ns; Loc. = LC_X3_Y3_N3; Fanout = 9; COMB Node = 'always2~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.372 ns" { control[4] always2~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.574 ns) 5.276 ns shift_register\[1\] 4 REG LC_X5_Y2_N0 2 " "Info: 4: + IC(2.002 ns) + CELL(0.574 ns) = 5.276 ns; Loc. = LC_X5_Y2_N0; Fanout = 2; REG Node = 'shift_register\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { always2~1 shift_register[1] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.482 ns ( 47.04 % ) " "Info: Total cell delay = 2.482 ns ( 47.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.794 ns ( 52.96 % ) " "Info: Total interconnect delay = 2.794 ns ( 52.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "5.276 ns" { pro_clk control[4] always2~1 shift_register[1] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "5.276 ns" { pro_clk {} pro_clk~combout {} control[4] {} always2~1 {} shift_register[1] {} } { 0.000ns 0.000ns 0.792ns 0.000ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.372ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 shift_register[2] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} shift_register[2] {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "5.276 ns" { pro_clk control[4] always2~1 shift_register[1] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "5.276 ns" { pro_clk {} pro_clk~combout {} control[4] {} always2~1 {} shift_register[1] {} } { 0.000ns 0.000ns 0.792ns 0.000ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.372ns 0.574ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns - " "Info: - Micro clock to output delay of source is 0.235 ns" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.245 ns - Shortest register register " "Info: - Shortest register to register delay is 1.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_register\[1\] 1 REG LC_X5_Y2_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N0; Fanout = 2; REG Node = 'shift_register\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_register[1] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.663 ns) 1.245 ns shift_register\[2\] 2 REG LC_X5_Y2_N5 2 " "Info: 2: + IC(0.582 ns) + CELL(0.663 ns) = 1.245 ns; Loc. = LC_X5_Y2_N5; Fanout = 2; REG Node = 'shift_register\[2\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.245 ns" { shift_register[1] shift_register[2] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.663 ns ( 53.25 % ) " "Info: Total cell delay = 0.663 ns ( 53.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.582 ns ( 46.75 % ) " "Info: Total interconnect delay = 0.582 ns ( 46.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.245 ns" { shift_register[1] shift_register[2] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "1.245 ns" { shift_register[1] {} shift_register[2] {} } { 0.000ns 0.582ns } { 0.000ns 0.663ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.138 ns + " "Info: + Micro hold delay of destination is 0.138 ns" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 68 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 shift_register[2] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} shift_register[2] {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "5.276 ns" { pro_clk control[4] always2~1 shift_register[1] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "5.276 ns" { pro_clk {} pro_clk~combout {} control[4] {} always2~1 {} shift_register[1] {} } { 0.000ns 0.000ns 0.792ns 0.000ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.372ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.245 ns" { shift_register[1] shift_register[2] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "1.245 ns" { shift_register[1] {} shift_register[2] {} } { 0.000ns 0.582ns } { 0.000ns 0.663ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "data_out\[7\] CS pro_clk 2.546 ns register " "Info: tsu for register \"data_out\[7\]\" (data pin = \"CS\", clock pin = \"pro_clk\") is 2.546 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.431 ns + Longest pin register " "Info: + Longest pin to register delay is 4.431 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.708 ns) 0.708 ns CS 1 PIN PIN_17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_17; Fanout = 4; PIN Node = 'CS'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { CS } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.391 ns) + CELL(0.125 ns) 3.224 ns data_out\[0\]~631 2 COMB LC_X2_Y2_N4 8 " "Info: 2: + IC(2.391 ns) + CELL(0.125 ns) = 3.224 ns; Loc. = LC_X2_Y2_N4; Fanout = 8; COMB Node = 'data_out\[0\]~631'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.516 ns" { CS data_out[0]~631 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.777 ns) 4.431 ns data_out\[7\] 3 REG LC_X2_Y2_N3 1 " "Info: 3: + IC(0.430 ns) + CELL(0.777 ns) = 4.431 ns; Loc. = LC_X2_Y2_N3; Fanout = 1; REG Node = 'data_out\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.207 ns" { data_out[0]~631 data_out[7] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.610 ns ( 36.33 % ) " "Info: Total cell delay = 1.610 ns ( 36.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.821 ns ( 63.67 % ) " "Info: Total interconnect delay = 2.821 ns ( 63.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.431 ns" { CS data_out[0]~631 data_out[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.431 ns" { CS {} CS~combout {} data_out[0]~631 {} data_out[7] {} } { 0.000ns 0.000ns 2.391ns 0.430ns } { 0.000ns 0.708ns 0.125ns 0.777ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk destination 2.093 ns - Shortest register " "Info: - Shortest clock path from clock \"pro_clk\" to destination register is 2.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.574 ns) 2.093 ns data_out\[7\] 2 REG LC_X2_Y2_N3 1 " "Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X2_Y2_N3; Fanout = 1; REG Node = 'data_out\[7\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.366 ns" { pro_clk data_out[7] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 62.16 % ) " "Info: Total cell delay = 1.301 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns ( 37.84 % ) " "Info: Total interconnect delay = 0.792 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.093 ns" { pro_clk data_out[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.093 ns" { pro_clk {} pro_clk~combout {} data_out[7] {} } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "4.431 ns" { CS data_out[0]~631 data_out[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "4.431 ns" { CS {} CS~combout {} data_out[0]~631 {} data_out[7] {} } { 0.000ns 0.000ns 2.391ns 0.430ns } { 0.000ns 0.708ns 0.125ns 0.777ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.093 ns" { pro_clk data_out[7] } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "2.093 ns" { pro_clk {} pro_clk~combout {} data_out[7] {} } { 0.000ns 0.000ns 0.792ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "pro_clk mosi mosi~reg0 13.949 ns register " "Info: tco from clock \"pro_clk\" to destination pin \"mosi\" through register \"mosi~reg0\" is 13.949 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pro_clk source 11.763 ns + Longest register " "Info: + Longest clock path from clock \"pro_clk\" to source register is 11.763 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns pro_clk 1 CLK PIN_14 34 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { pro_clk } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.792 ns) + CELL(0.809 ns) 2.328 ns control\[1\] 2 REG LC_X3_Y2_N9 4 " "Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X3_Y2_N9; Fanout = 4; REG Node = 'control\[1\]'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { pro_clk control[1] } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 129 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.238 ns) + CELL(0.571 ns) 4.137 ns Mux0~53 3 COMB LC_X3_Y2_N8 1 " "Info: 3: + IC(1.238 ns) + CELL(0.571 ns) = 4.137 ns; Loc. = LC_X3_Y2_N8; Fanout = 1; COMB Node = 'Mux0~53'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.809 ns" { control[1] Mux0~53 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.191 ns) + CELL(0.125 ns) 4.453 ns Mux0~54 4 COMB LC_X3_Y2_N9 1 " "Info: 4: + IC(0.191 ns) + CELL(0.125 ns) = 4.453 ns; Loc. = LC_X3_Y2_N9; Fanout = 1; COMB Node = 'Mux0~54'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "0.316 ns" { Mux0~53 Mux0~54 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.462 ns) 6.017 ns Mux0 5 COMB LC_X4_Y2_N2 1 " "Info: 5: + IC(1.102 ns) + CELL(0.462 ns) = 6.017 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Mux0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.564 ns" { Mux0~54 Mux0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.078 ns) + CELL(0.809 ns) 7.904 ns sclk~reg0 6 REG LC_X4_Y3_N2 8 " "Info: 6: + IC(1.078 ns) + CELL(0.809 ns) = 7.904 ns; Loc. = LC_X4_Y3_N2; Fanout = 8; REG Node = 'sclk~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.887 ns" { Mux0 sclk~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 109 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.462 ns) 9.187 ns always2~1 7 COMB LC_X3_Y3_N3 9 " "Info: 7: + IC(0.821 ns) + CELL(0.462 ns) = 9.187 ns; Loc. = LC_X3_Y3_N3; Fanout = 9; COMB Node = 'always2~1'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.283 ns" { sclk~reg0 always2~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(0.574 ns) 11.763 ns mosi~reg0 8 REG LC_X7_Y4_N3 1 " "Info: 8: + IC(2.002 ns) + CELL(0.574 ns) = 11.763 ns; Loc. = LC_X7_Y4_N3; Fanout = 1; REG Node = 'mosi~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { always2~1 mosi~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 77 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.539 ns ( 38.59 % ) " "Info: Total cell delay = 4.539 ns ( 38.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.224 ns ( 61.41 % ) " "Info: Total interconnect delay = 7.224 ns ( 61.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 mosi~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} mosi~reg0 {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 77 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.951 ns + Longest register pin " "Info: + Longest register to pin delay is 1.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mosi~reg0 1 REG LC_X7_Y4_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N3; Fanout = 1; REG Node = 'mosi~reg0'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "" { mosi~reg0 } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 77 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.497 ns) + CELL(1.454 ns) 1.951 ns mosi 2 PIN PIN_73 0 " "Info: 2: + IC(0.497 ns) + CELL(1.454 ns) = 1.951 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'mosi'" {  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { mosi~reg0 mosi } "NODE_NAME" } } { "SPI_Master.v" "" { Text "D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 74.53 % ) " "Info: Total cell delay = 1.454 ns ( 74.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.497 ns ( 25.47 % ) " "Info: Total interconnect delay = 0.497 ns ( 25.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { mosi~reg0 mosi } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "1.951 ns" { mosi~reg0 {} mosi {} } { 0.000ns 0.497ns } { 0.000ns 1.454ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "11.763 ns" { pro_clk control[1] Mux0~53 Mux0~54 Mux0 sclk~reg0 always2~1 mosi~reg0 } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "11.763 ns" { pro_clk {} pro_clk~combout {} control[1] {} Mux0~53 {} Mux0~54 {} Mux0 {} sclk~reg0 {} always2~1 {} mosi~reg0 {} } { 0.000ns 0.000ns 0.792ns 1.238ns 0.191ns 1.102ns 1.078ns 0.821ns 2.002ns } { 0.000ns 0.727ns 0.809ns 0.571ns 0.125ns 0.462ns 0.809ns 0.462ns 0.574ns } "" } } { "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72_cc/quartus/bin/TimingClosureFloorplan.fld" "" "1.951 ns" { mosi~reg0 mosi } "NODE_NAME" } } { "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72_cc/quartus/bin/Technology_Viewer.qrui" "1.951 ns" { mosi~reg0 {} mosi {} } { 0.000ns 0.497ns } { 0.000ns 1.454ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}