spi_master.map.rpt

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

;     -- Combinational with no register       ; 21      ;
;     -- Register only                        ; 35      ;
;     -- Combinational with a register        ; 22      ;
;                                             ;         ;
; Logic element usage by number of LUT inputs ;         ;
;     -- 4 input functions                    ; 17      ;
;     -- 3 input functions                    ; 7       ;
;     -- 2 input functions                    ; 15      ;
;     -- 1 input functions                    ; 3       ;
;     -- 0 input functions                    ; 1       ;
;                                             ;         ;
; Logic elements by mode                      ;         ;
;     -- normal mode                          ; 72      ;
;     -- arithmetic mode                      ; 6       ;
;     -- qfbk mode                            ; 0       ;
;     -- register cascade mode                ; 0       ;
;     -- synchronous clear/load mode          ; 1       ;
;     -- asynchronous clear/load mode         ; 14      ;
;                                             ;         ;
; Total registers                             ; 57      ;
; Total logic cells in carry chains           ; 7       ;
; I/O pins                                    ; 25      ;
; Maximum fan-out node                        ; pro_clk ;
; Maximum fan-out                             ; 34      ;
; Total fan-out                               ; 296     ;
; Average fan-out                             ; 2.87    ;
+---------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |SPI_Master                ; 78 (78)     ; 57           ; 0           ; 0            ; 0       ; 0         ; 0         ; 25   ; 0            ; 21 (21)      ; 35 (35)           ; 22 (22)          ; 7 (7)           ; 0 (0)      ; |SPI_Master         ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; status[1..7]                          ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 7 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 57    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 1     ;
; Number of registers using Asynchronous Clear ; 5     ;
; Number of registers using Asynchronous Load  ; 9     ;
; Number of registers using Clock Enable       ; 31    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; slave_cs                               ; 23      ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 6:1                ; 7 bits    ; 28 LEs        ; 14 LEs               ; 14 LEs                 ; Yes        ; |SPI_Master|data_out[1]    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------+
; Analysis & Synthesis INI Usage                                 ;
+----------------------+-----------------------------------------+
; Option               ; Usage                                   ;
+----------------------+-----------------------------------------+
; Initialization file: ; c:/altera/72_cc/quartus/bin/quartus.ini ;
; debug_msg            ; OFF                                     ;
+----------------------+-----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 16:41:50 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SPI_Master -c SPI_Master
Warning (10261): Verilog HDL Event Control warning at SPI_Master.v(62): Event Control contains a complex event expression
Warning (10261): Verilog HDL Event Control warning at SPI_Master.v(72): Event Control contains a complex event expression
Info: Found 1 design units, including 1 entities, in source file SPI_Master.v
    Info: Found entity 1: SPI_Master
Info: Elaborating entity "SPI_Master" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at SPI_Master.v(58): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at SPI_Master.v(124): truncated value with size 32 to match size of target (4)
Warning (14130): Reduced register "status[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "status[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "status[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "status[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "status[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "status[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "status[1]" with stuck data_in port to stuck value GND
Info: Clock multiplexers have been protected
Info: Implemented 103 device resources after synthesis - the final resource count might be different
    Info: Implemented 7 input pins
    Info: Implemented 10 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 78 logic cells
Info: Generated suppressed messages file D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.map.smsg
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Allocated 147 megabytes of memory during processing
    Info: Processing ended: Thu Nov 22 16:41:55 2007
    Info: Elapsed time: 00:00:05


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/Altera/MAXIIZ update/Design example/AN485/quartus/SPI_Master.map.smsg.