spi_master.tan.rpt

AN485_CH-MAX II CPLD 中的串行外设接口主机（verilog SPI）

; N/A           ; None        ; -1.951 ns ; RD          ; data_out[4]       ; pro_clk  ;
; N/A           ; None        ; -1.951 ns ; RD          ; data_out[2]       ; pro_clk  ;
; N/A           ; None        ; -1.951 ns ; RD          ; data_out[1]       ; pro_clk  ;
; N/A           ; None        ; -1.977 ns ; addr[0]     ; control[3]        ; pro_clk  ;
; N/A           ; None        ; -1.977 ns ; addr[0]     ; control[5]        ; pro_clk  ;
; N/A           ; None        ; -1.977 ns ; addr[0]     ; control[6]        ; pro_clk  ;
; N/A           ; None        ; -1.977 ns ; addr[0]     ; control[7]        ; pro_clk  ;
; N/A           ; None        ; -1.977 ns ; addr[0]     ; control[4]        ; pro_clk  ;
; N/A           ; None        ; -1.984 ns ; addr[0]     ; control[2]        ; pro_clk  ;
; N/A           ; None        ; -1.986 ns ; CS          ; data_out[0]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[7]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[6]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[5]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[3]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[4]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[2]       ; pro_clk  ;
; N/A           ; None        ; -2.004 ns ; addr[0]     ; data_out[1]       ; pro_clk  ;
; N/A           ; None        ; -2.018 ns ; WR          ; control[3]        ; pro_clk  ;
; N/A           ; None        ; -2.018 ns ; WR          ; control[5]        ; pro_clk  ;
; N/A           ; None        ; -2.018 ns ; WR          ; control[6]        ; pro_clk  ;
; N/A           ; None        ; -2.018 ns ; WR          ; control[7]        ; pro_clk  ;
; N/A           ; None        ; -2.018 ns ; WR          ; control[4]        ; pro_clk  ;
; N/A           ; None        ; -2.025 ns ; WR          ; control[2]        ; pro_clk  ;
; N/A           ; None        ; -2.109 ns ; CS          ; control[3]        ; pro_clk  ;
; N/A           ; None        ; -2.109 ns ; CS          ; control[5]        ; pro_clk  ;
; N/A           ; None        ; -2.109 ns ; CS          ; control[6]        ; pro_clk  ;
; N/A           ; None        ; -2.109 ns ; CS          ; control[7]        ; pro_clk  ;
; N/A           ; None        ; -2.109 ns ; CS          ; control[4]        ; pro_clk  ;
; N/A           ; None        ; -2.116 ns ; CS          ; control[2]        ; pro_clk  ;
; N/A           ; None        ; -2.137 ns ; addr[1]     ; control[3]        ; pro_clk  ;
; N/A           ; None        ; -2.137 ns ; addr[1]     ; control[5]        ; pro_clk  ;
; N/A           ; None        ; -2.137 ns ; addr[1]     ; control[6]        ; pro_clk  ;
; N/A           ; None        ; -2.137 ns ; addr[1]     ; control[7]        ; pro_clk  ;
; N/A           ; None        ; -2.137 ns ; addr[1]     ; control[4]        ; pro_clk  ;
; N/A           ; None        ; -2.144 ns ; addr[1]     ; control[2]        ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[7]       ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[6]       ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[5]       ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[3]       ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[4]       ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[2]       ; pro_clk  ;
; N/A           ; None        ; -2.200 ns ; CS          ; data_out[1]       ; pro_clk  ;
+---------------+-------------+-----------+-------------+-------------------+----------+


+----------------------------------------------------------------+
; Timing Analyzer INI Usage                                      ;
+----------------------+-----------------------------------------+
; Option               ; Usage                                   ;
+----------------------+-----------------------------------------+
; Initialization file: ; c:/altera/72_cc/quartus/bin/quartus.ini ;
; debug_msg            ; OFF                                     ;
+----------------------+-----------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Thu Nov 22 16:42:09 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off SPI_Master -c SPI_Master
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "pro_clk" is an undefined clock
Warning: Found 21 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux0~55" as buffer
    Info: Detected ripple clock "control[0]" as buffer
    Info: Detected ripple clock "control[1]" as buffer
    Info: Detected gated clock "Mux0~53" as buffer
    Info: Detected ripple clock "control[2]" as buffer
    Info: Detected gated clock "Mux0~56" as buffer
    Info: Detected gated clock "Mux0~54" as buffer
    Info: Detected ripple clock "clk_divide[7]" as buffer
    Info: Detected ripple clock "clk_divide[6]" as buffer
    Info: Detected ripple clock "clk_divide[5]" as buffer
    Info: Detected ripple clock "clk_divide[4]" as buffer
    Info: Detected ripple clock "clk_divide[3]" as buffer
    Info: Detected ripple clock "clk_divide[2]" as buffer
    Info: Detected ripple clock "clk_divide[1]" as buffer
    Info: Detected ripple clock "clk_divide[0]" as buffer
    Info: Detected ripple clock "control[4]" as buffer
    Info: Detected gated clock "Mux0" as buffer
    Info: Detected ripple clock "slave_cs" as buffer
    Info: Detected ripple clock "control[3]" as buffer
    Info: Detected ripple clock "sclk~reg0" as buffer
    Info: Detected gated clock "always2~1" as buffer
Info: Clock "pro_clk" has Internal fmax of 58.71 MHz between source register "shift_register[7]" and destination register "rxdata[7]" (period= 17.032 ns)
    Info: + Longest register to register delay is 0.928 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; REG Node = 'shift_register[7]'
        Info: 2: + IC(0.559 ns) + CELL(0.369 ns) = 0.928 ns; Loc. = LC_X3_Y4_N9; Fanout = 1; REG Node = 'rxdata[7]'
        Info: Total cell delay = 0.369 ns ( 39.76 % )
        Info: Total interconnect delay = 0.559 ns ( 60.24 % )
    Info: - Smallest clock skew is -7.145 ns
        Info: + Shortest clock path from clock "pro_clk" to destination register is 4.618 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'
            Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X2_Y3_N7; Fanout = 23; REG Node = 'slave_cs'
            Info: 3: + IC(1.716 ns) + CELL(0.574 ns) = 4.618 ns; Loc. = LC_X3_Y4_N9; Fanout = 1; REG Node = 'rxdata[7]'
            Info: Total cell delay = 2.110 ns ( 45.69 % )
            Info: Total interconnect delay = 2.508 ns ( 54.31 % )
        Info: - Longest clock path from clock "pro_clk" to source register is 11.763 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'
            Info: 2: + IC(0.792 ns) + CELL(0.809 ns) = 2.328 ns; Loc. = LC_X3_Y2_N9; Fanout = 4; REG Node = 'control[1]'
            Info: 3: + IC(1.238 ns) + CELL(0.571 ns) = 4.137 ns; Loc. = LC_X3_Y2_N8; Fanout = 1; COMB Node = 'Mux0~53'
            Info: 4: + IC(0.191 ns) + CELL(0.125 ns) = 4.453 ns; Loc. = LC_X3_Y2_N9; Fanout = 1; COMB Node = 'Mux0~54'
            Info: 5: + IC(1.102 ns) + CELL(0.462 ns) = 6.017 ns; Loc. = LC_X4_Y2_N2; Fanout = 1; COMB Node = 'Mux0'
            Info: 6: + IC(1.078 ns) + CELL(0.809 ns) = 7.904 ns; Loc. = LC_X4_Y3_N2; Fanout = 8; REG Node = 'sclk~reg0'
            Info: 7: + IC(0.821 ns) + CELL(0.462 ns) = 9.187 ns; Loc. = LC_X3_Y3_N3; Fanout = 9; COMB Node = 'always2~1'
            Info: 8: + IC(2.002 ns) + CELL(0.574 ns) = 11.763 ns; Loc. = LC_X3_Y4_N8; Fanout = 2; REG Node = 'shift_register[7]'
            Info: Total cell delay = 4.539 ns ( 38.59 % )
            Info: Total interconnect delay = 7.224 ns ( 61.41 % )
    Info: + Micro clock to output delay of source is 0.235 ns
    Info: + Micro setup delay of destination is 0.208 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two
Warning: Circuit may not operate. Detected 21 non-operational path(s) clocked by clock "pro_clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "shift_register[1]" and destination pin or register "shift_register[2]" for clock "pro_clk" (Hold time is 5.145 ns)
    Info: + Largest clock skew is 6.487 ns
        Info: + Longest clock path from clock "pro_clk" to destination register is 11.763 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 34; CLK Node = 'pro_clk'
            Info: 2