_primary.vhd

用verlog hdl开发的SPI 的源码

library verilog;
use verilog.vl_types.all;
entity i2s_master is
    port(
        ws              : out    vl_logic;
        sda             : inout  vl_logic;
        sck_out         : out    vl_logic;
        command_ack_ack : in     vl_logic;
        data_ack_ack    : in     vl_logic;
        buffer_com3     : in     vl_logic_vector(6 downto 0);
        com3            : in     vl_logic;
        command_ack     : out    vl_logic;
        data3           : in     vl_logic;
        data_rec_ack    : in     vl_logic;
        status_reg      : out    vl_logic_vector(2 downto 0);
        data_from_i2s   : out    vl_logic_vector(15 downto 0);
        buffer_data3    : in     vl_logic_vector(15 downto 0);
        done_rec_i2s    : out    vl_logic;
        data_ack        : out    vl_logic;
        sck             : in     vl_logic
    );
end i2s_master;