_primary.vhd

来自「用verlog hdl开发的SPI 的源码」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity spi_to_i2s is
    port(
        SPI_sclk        : in     vl_logic;
        SPI_cs          : in     vl_logic;
        SPI_miso        : out    vl_logic;
        sck_w           : in     vl_logic;
        SPI_mosi        : in     vl_logic;
        I2S_sda         : inout  vl_logic;
        I2S_sck         : out    vl_logic;
        I2S_ws          : out    vl_logic
    );
end spi_to_i2s;