_primary.vhd

来自「用verlog hdl开发的SPI 的源码」· VHDL 代码 · 共 23 行

library verilog;
use verilog.vl_types.all;
entity spi_slave is
    port(
        miso            : out    vl_logic;
        mosi            : in     vl_logic;
        cs              : in     vl_logic;
        sclk            : in     vl_logic;
        buffer_com3     : out    vl_logic_vector(6 downto 0);
        command_ack_ack : out    vl_logic;
        data_ack_ack    : out    vl_logic;
        data_rec_ack    : out    vl_logic;
        status          : in     vl_logic_vector(2 downto 0);
        buffer_data3    : out    vl_logic_vector(15 downto 0);
        data_ack        : in     vl_logic;
        command_ack     : in     vl_logic;
        data_out        : in     vl_logic_vector(15 downto 0);
        com3            : out    vl_logic;
        data3           : out    vl_logic;
        done_rec_i2s    : in     vl_logic
    );
end spi_slave;