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📁 CPLD/FPGA常用模块与综合系统设计实例光盘程序
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stratixii_io \RX_FIFO_RST[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_FIFO_RST~combout [5]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_FIFO_RST[5]));
// synopsys translate_off
defparam \RX_FIFO_RST[5]~I .ddio_mode = "none";
defparam \RX_FIFO_RST[5]~I .ddioinclk_input = "negated_inclk";
defparam \RX_FIFO_RST[5]~I .dqs_delay_buffer_mode = "none";
defparam \RX_FIFO_RST[5]~I .dqs_out_mode = "none";
defparam \RX_FIFO_RST[5]~I .inclk_input = "normal";
defparam \RX_FIFO_RST[5]~I .input_async_reset = "none";
defparam \RX_FIFO_RST[5]~I .input_power_up = "low";
defparam \RX_FIFO_RST[5]~I .input_register_mode = "none";
defparam \RX_FIFO_RST[5]~I .input_sync_reset = "none";
defparam \RX_FIFO_RST[5]~I .oe_async_reset = "none";
defparam \RX_FIFO_RST[5]~I .oe_power_up = "low";
defparam \RX_FIFO_RST[5]~I .oe_register_mode = "none";
defparam \RX_FIFO_RST[5]~I .oe_sync_reset = "none";
defparam \RX_FIFO_RST[5]~I .operation_mode = "input";
defparam \RX_FIFO_RST[5]~I .output_async_reset = "none";
defparam \RX_FIFO_RST[5]~I .output_power_up = "low";
defparam \RX_FIFO_RST[5]~I .output_register_mode = "none";
defparam \RX_FIFO_RST[5]~I .output_sync_reset = "none";
defparam \RX_FIFO_RST[5]~I .sim_dqs_delay_increment = 0;
defparam \RX_FIFO_RST[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_FIFO_RST[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_N22
stratixii_io \RX_CH_DATA_ALIGN[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_CH_DATA_ALIGN~combout [5]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_CH_DATA_ALIGN[5]));
// synopsys translate_off
defparam \RX_CH_DATA_ALIGN[5]~I .ddio_mode = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .ddioinclk_input = "negated_inclk";
defparam \RX_CH_DATA_ALIGN[5]~I .dqs_delay_buffer_mode = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .dqs_out_mode = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .inclk_input = "normal";
defparam \RX_CH_DATA_ALIGN[5]~I .input_async_reset = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .input_power_up = "low";
defparam \RX_CH_DATA_ALIGN[5]~I .input_register_mode = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .input_sync_reset = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .oe_async_reset = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .oe_power_up = "low";
defparam \RX_CH_DATA_ALIGN[5]~I .oe_register_mode = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .oe_sync_reset = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .operation_mode = "input";
defparam \RX_CH_DATA_ALIGN[5]~I .output_async_reset = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .output_power_up = "low";
defparam \RX_CH_DATA_ALIGN[5]~I .output_register_mode = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .output_sync_reset = "none";
defparam \RX_CH_DATA_ALIGN[5]~I .sim_dqs_delay_increment = 0;
defparam \RX_CH_DATA_ALIGN[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_CH_DATA_ALIGN[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_L25
stratixii_io \RX_CDA_RST[5]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_CDA_RST~combout [5]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_CDA_RST[5]));
// synopsys translate_off
defparam \RX_CDA_RST[5]~I .ddio_mode = "none";
defparam \RX_CDA_RST[5]~I .ddioinclk_input = "negated_inclk";
defparam \RX_CDA_RST[5]~I .dqs_delay_buffer_mode = "none";
defparam \RX_CDA_RST[5]~I .dqs_out_mode = "none";
defparam \RX_CDA_RST[5]~I .inclk_input = "normal";
defparam \RX_CDA_RST[5]~I .input_async_reset = "none";
defparam \RX_CDA_RST[5]~I .input_power_up = "low";
defparam \RX_CDA_RST[5]~I .input_register_mode = "none";
defparam \RX_CDA_RST[5]~I .input_sync_reset = "none";
defparam \RX_CDA_RST[5]~I .oe_async_reset = "none";
defparam \RX_CDA_RST[5]~I .oe_power_up = "low";
defparam \RX_CDA_RST[5]~I .oe_register_mode = "none";
defparam \RX_CDA_RST[5]~I .oe_sync_reset = "none";
defparam \RX_CDA_RST[5]~I .operation_mode = "input";
defparam \RX_CDA_RST[5]~I .output_async_reset = "none";
defparam \RX_CDA_RST[5]~I .output_power_up = "low";
defparam \RX_CDA_RST[5]~I .output_register_mode = "none";
defparam \RX_CDA_RST[5]~I .output_sync_reset = "none";
defparam \RX_CDA_RST[5]~I .sim_dqs_delay_increment = 0;
defparam \RX_CDA_RST[5]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_CDA_RST[5]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_W26
stratixii_io \RX_IN[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_IN~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_IN[4]));
// synopsys translate_off
defparam \RX_IN[4]~I .ddio_mode = "none";
defparam \RX_IN[4]~I .ddioinclk_input = "negated_inclk";
defparam \RX_IN[4]~I .dqs_delay_buffer_mode = "none";
defparam \RX_IN[4]~I .dqs_out_mode = "none";
defparam \RX_IN[4]~I .inclk_input = "normal";
defparam \RX_IN[4]~I .input_async_reset = "none";
defparam \RX_IN[4]~I .input_power_up = "low";
defparam \RX_IN[4]~I .input_register_mode = "none";
defparam \RX_IN[4]~I .input_sync_reset = "none";
defparam \RX_IN[4]~I .oe_async_reset = "none";
defparam \RX_IN[4]~I .oe_power_up = "low";
defparam \RX_IN[4]~I .oe_register_mode = "none";
defparam \RX_IN[4]~I .oe_sync_reset = "none";
defparam \RX_IN[4]~I .operation_mode = "input";
defparam \RX_IN[4]~I .output_async_reset = "none";
defparam \RX_IN[4]~I .output_power_up = "low";
defparam \RX_IN[4]~I .output_register_mode = "none";
defparam \RX_IN[4]~I .output_sync_reset = "none";
defparam \RX_IN[4]~I .sim_dqs_delay_increment = 0;
defparam \RX_IN[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_IN[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_P23
stratixii_io \RX_RESET[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_RESET~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_RESET[4]));
// synopsys translate_off
defparam \RX_RESET[4]~I .ddio_mode = "none";
defparam \RX_RESET[4]~I .ddioinclk_input = "negated_inclk";
defparam \RX_RESET[4]~I .dqs_delay_buffer_mode = "none";
defparam \RX_RESET[4]~I .dqs_out_mode = "none";
defparam \RX_RESET[4]~I .inclk_input = "normal";
defparam \RX_RESET[4]~I .input_async_reset = "none";
defparam \RX_RESET[4]~I .input_power_up = "low";
defparam \RX_RESET[4]~I .input_register_mode = "none";
defparam \RX_RESET[4]~I .input_sync_reset = "none";
defparam \RX_RESET[4]~I .oe_async_reset = "none";
defparam \RX_RESET[4]~I .oe_power_up = "low";
defparam \RX_RESET[4]~I .oe_register_mode = "none";
defparam \RX_RESET[4]~I .oe_sync_reset = "none";
defparam \RX_RESET[4]~I .operation_mode = "input";
defparam \RX_RESET[4]~I .output_async_reset = "none";
defparam \RX_RESET[4]~I .output_power_up = "low";
defparam \RX_RESET[4]~I .output_register_mode = "none";
defparam \RX_RESET[4]~I .output_sync_reset = "none";
defparam \RX_RESET[4]~I .sim_dqs_delay_increment = 0;
defparam \RX_RESET[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_RESET[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_H23
stratixii_io \RX_DPLL_HOLD[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_DPLL_HOLD~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_DPLL_HOLD[4]));
// synopsys translate_off
defparam \RX_DPLL_HOLD[4]~I .ddio_mode = "none";
defparam \RX_DPLL_HOLD[4]~I .ddioinclk_input = "negated_inclk";
defparam \RX_DPLL_HOLD[4]~I .dqs_delay_buffer_mode = "none";
defparam \RX_DPLL_HOLD[4]~I .dqs_out_mode = "none";
defparam \RX_DPLL_HOLD[4]~I .inclk_input = "normal";
defparam \RX_DPLL_HOLD[4]~I .input_async_reset = "none";
defparam \RX_DPLL_HOLD[4]~I .input_power_up = "low";
defparam \RX_DPLL_HOLD[4]~I .input_register_mode = "none";
defparam \RX_DPLL_HOLD[4]~I .input_sync_reset = "none";
defparam \RX_DPLL_HOLD[4]~I .oe_async_reset = "none";
defparam \RX_DPLL_HOLD[4]~I .oe_power_up = "low";
defparam \RX_DPLL_HOLD[4]~I .oe_register_mode = "none";
defparam \RX_DPLL_HOLD[4]~I .oe_sync_reset = "none";
defparam \RX_DPLL_HOLD[4]~I .operation_mode = "input";
defparam \RX_DPLL_HOLD[4]~I .output_async_reset = "none";
defparam \RX_DPLL_HOLD[4]~I .output_power_up = "low";
defparam \RX_DPLL_HOLD[4]~I .output_register_mode = "none";
defparam \RX_DPLL_HOLD[4]~I .output_sync_reset = "none";
defparam \RX_DPLL_HOLD[4]~I .sim_dqs_delay_increment = 0;
defparam \RX_DPLL_HOLD[4]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_DPLL_HOLD[4]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_N19
stratixii_io \RX_DPLL_EN[4]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_DPLL_EN~combout [4]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_DPLL_EN[4]));
// synopsys translate_off
defparam \RX_DPLL_EN[4]~I .ddio_mode = "none";
defparam \RX_DPLL_EN[4]~I .ddioinclk_input = "negated_inclk";
defparam \RX_DPLL_EN[4]~I .dqs_delay_buffer_mode = "none";
defparam \RX_DPLL_EN[4]~I .dqs_out_mode = "none";
defparam \RX_DPLL_EN[4]~I .inclk_input = "normal";
defparam \RX_DPLL_EN[4]~I .input_async_reset = "none";
defparam \RX_DPLL_EN[4]~I .input_power_up = "low";
defparam \RX_DPLL_EN[4]~I .input_register_mode = "none";
defparam \RX_DPLL_EN[4]~I .input_sync_reset = "none";
defparam \RX_DPLL_EN[4]~I .oe_async_reset = "none";
defparam \RX_DPLL_EN[4]~I .oe_power_up = "low";
defparam \RX_DPLL_EN[4]~I .oe_register_mode = "none";
defparam \RX_DPLL_EN[4]~I .oe_sync_reset = "none";
defparam \RX_DPLL_EN[4]~I .operation_mode = "input";
defparam \
上一页 1 2 3 45
💿 文件大小 17053 K
👤 上传用户 foreverlovely
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#CPLD #FPGA #模块 #光盘
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