altlvds_stratixii.vo

来自「CPLD/FPGA常用模块与综合系统设计实例光盘程序」· VO 代码 · 共 1,717 行 · 第 1/5 页

VO
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	.devoe(devoe),
	.combout(\PLL_ENABLE~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(PLL_ENABLE));
// synopsys translate_off
defparam \PLL_ENABLE~I .ddio_mode = "none";
defparam \PLL_ENABLE~I .ddioinclk_input = "negated_inclk";
defparam \PLL_ENABLE~I .dqs_delay_buffer_mode = "none";
defparam \PLL_ENABLE~I .dqs_out_mode = "none";
defparam \PLL_ENABLE~I .inclk_input = "normal";
defparam \PLL_ENABLE~I .input_async_reset = "none";
defparam \PLL_ENABLE~I .input_power_up = "low";
defparam \PLL_ENABLE~I .input_register_mode = "none";
defparam \PLL_ENABLE~I .input_sync_reset = "none";
defparam \PLL_ENABLE~I .oe_async_reset = "none";
defparam \PLL_ENABLE~I .oe_power_up = "low";
defparam \PLL_ENABLE~I .oe_register_mode = "none";
defparam \PLL_ENABLE~I .oe_sync_reset = "none";
defparam \PLL_ENABLE~I .operation_mode = "input";
defparam \PLL_ENABLE~I .output_async_reset = "none";
defparam \PLL_ENABLE~I .output_power_up = "low";
defparam \PLL_ENABLE~I .output_register_mode = "none";
defparam \PLL_ENABLE~I .output_sync_reset = "none";
defparam \PLL_ENABLE~I .sim_dqs_delay_increment = 0;
defparam \PLL_ENABLE~I .sim_dqs_intrinsic_delay = 0;
defparam \PLL_ENABLE~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_L21
stratixii_io \PLL_ARESET~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\PLL_ARESET~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(PLL_ARESET));
// synopsys translate_off
defparam \PLL_ARESET~I .ddio_mode = "none";
defparam \PLL_ARESET~I .ddioinclk_input = "negated_inclk";
defparam \PLL_ARESET~I .dqs_delay_buffer_mode = "none";
defparam \PLL_ARESET~I .dqs_out_mode = "none";
defparam \PLL_ARESET~I .inclk_input = "normal";
defparam \PLL_ARESET~I .input_async_reset = "none";
defparam \PLL_ARESET~I .input_power_up = "low";
defparam \PLL_ARESET~I .input_register_mode = "none";
defparam \PLL_ARESET~I .input_sync_reset = "none";
defparam \PLL_ARESET~I .oe_async_reset = "none";
defparam \PLL_ARESET~I .oe_power_up = "low";
defparam \PLL_ARESET~I .oe_register_mode = "none";
defparam \PLL_ARESET~I .oe_sync_reset = "none";
defparam \PLL_ARESET~I .operation_mode = "input";
defparam \PLL_ARESET~I .output_async_reset = "none";
defparam \PLL_ARESET~I .output_power_up = "low";
defparam \PLL_ARESET~I .output_register_mode = "none";
defparam \PLL_ARESET~I .output_sync_reset = "none";
defparam \PLL_ARESET~I .sim_dqs_delay_increment = 0;
defparam \PLL_ARESET~I .sim_dqs_intrinsic_delay = 0;
defparam \PLL_ARESET~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_R26
stratixii_io \CLK_IN_500MHZ~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\CLK_IN_500MHZ~combout ),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(CLK_IN_500MHZ));
// synopsys translate_off
defparam \CLK_IN_500MHZ~I .ddio_mode = "none";
defparam \CLK_IN_500MHZ~I .ddioinclk_input = "negated_inclk";
defparam \CLK_IN_500MHZ~I .dqs_delay_buffer_mode = "none";
defparam \CLK_IN_500MHZ~I .dqs_out_mode = "none";
defparam \CLK_IN_500MHZ~I .inclk_input = "normal";
defparam \CLK_IN_500MHZ~I .input_async_reset = "none";
defparam \CLK_IN_500MHZ~I .input_power_up = "low";
defparam \CLK_IN_500MHZ~I .input_register_mode = "none";
defparam \CLK_IN_500MHZ~I .input_sync_reset = "none";
defparam \CLK_IN_500MHZ~I .oe_async_reset = "none";
defparam \CLK_IN_500MHZ~I .oe_power_up = "low";
defparam \CLK_IN_500MHZ~I .oe_register_mode = "none";
defparam \CLK_IN_500MHZ~I .oe_sync_reset = "none";
defparam \CLK_IN_500MHZ~I .operation_mode = "input";
defparam \CLK_IN_500MHZ~I .output_async_reset = "none";
defparam \CLK_IN_500MHZ~I .output_power_up = "low";
defparam \CLK_IN_500MHZ~I .output_register_mode = "none";
defparam \CLK_IN_500MHZ~I .output_sync_reset = "none";
defparam \CLK_IN_500MHZ~I .sim_dqs_delay_increment = 0;
defparam \CLK_IN_500MHZ~I .sim_dqs_intrinsic_delay = 0;
defparam \CLK_IN_500MHZ~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_T25
stratixii_io \RX_IN[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_IN~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_IN[7]));
// synopsys translate_off
defparam \RX_IN[7]~I .ddio_mode = "none";
defparam \RX_IN[7]~I .ddioinclk_input = "negated_inclk";
defparam \RX_IN[7]~I .dqs_delay_buffer_mode = "none";
defparam \RX_IN[7]~I .dqs_out_mode = "none";
defparam \RX_IN[7]~I .inclk_input = "normal";
defparam \RX_IN[7]~I .input_async_reset = "none";
defparam \RX_IN[7]~I .input_power_up = "low";
defparam \RX_IN[7]~I .input_register_mode = "none";
defparam \RX_IN[7]~I .input_sync_reset = "none";
defparam \RX_IN[7]~I .oe_async_reset = "none";
defparam \RX_IN[7]~I .oe_power_up = "low";
defparam \RX_IN[7]~I .oe_register_mode = "none";
defparam \RX_IN[7]~I .oe_sync_reset = "none";
defparam \RX_IN[7]~I .operation_mode = "input";
defparam \RX_IN[7]~I .output_async_reset = "none";
defparam \RX_IN[7]~I .output_power_up = "low";
defparam \RX_IN[7]~I .output_register_mode = "none";
defparam \RX_IN[7]~I .output_sync_reset = "none";
defparam \RX_IN[7]~I .sim_dqs_delay_increment = 0;
defparam \RX_IN[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_IN[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_H26
stratixii_io \RX_RESET[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_RESET~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_RESET[7]));
// synopsys translate_off
defparam \RX_RESET[7]~I .ddio_mode = "none";
defparam \RX_RESET[7]~I .ddioinclk_input = "negated_inclk";
defparam \RX_RESET[7]~I .dqs_delay_buffer_mode = "none";
defparam \RX_RESET[7]~I .dqs_out_mode = "none";
defparam \RX_RESET[7]~I .inclk_input = "normal";
defparam \RX_RESET[7]~I .input_async_reset = "none";
defparam \RX_RESET[7]~I .input_power_up = "low";
defparam \RX_RESET[7]~I .input_register_mode = "none";
defparam \RX_RESET[7]~I .input_sync_reset = "none";
defparam \RX_RESET[7]~I .oe_async_reset = "none";
defparam \RX_RESET[7]~I .oe_power_up = "low";
defparam \RX_RESET[7]~I .oe_register_mode = "none";
defparam \RX_RESET[7]~I .oe_sync_reset = "none";
defparam \RX_RESET[7]~I .operation_mode = "input";
defparam \RX_RESET[7]~I .output_async_reset = "none";
defparam \RX_RESET[7]~I .output_power_up = "low";
defparam \RX_RESET[7]~I .output_register_mode = "none";
defparam \RX_RESET[7]~I .output_sync_reset = "none";
defparam \RX_RESET[7]~I .sim_dqs_delay_increment = 0;
defparam \RX_RESET[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_RESET[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_M24
stratixii_io \RX_DPLL_HOLD[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_DPLL_HOLD~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_DPLL_HOLD[7]));
// synopsys translate_off
defparam \RX_DPLL_HOLD[7]~I .ddio_mode = "none";
defparam \RX_DPLL_HOLD[7]~I .ddioinclk_input = "negated_inclk";
defparam \RX_DPLL_HOLD[7]~I .dqs_delay_buffer_mode = "none";
defparam \RX_DPLL_HOLD[7]~I .dqs_out_mode = "none";
defparam \RX_DPLL_HOLD[7]~I .inclk_input = "normal";
defparam \RX_DPLL_HOLD[7]~I .input_async_reset = "none";
defparam \RX_DPLL_HOLD[7]~I .input_power_up = "low";
defparam \RX_DPLL_HOLD[7]~I .input_register_mode = "none";
defparam \RX_DPLL_HOLD[7]~I .input_sync_reset = "none";
defparam \RX_DPLL_HOLD[7]~I .oe_async_reset = "none";
defparam \RX_DPLL_HOLD[7]~I .oe_power_up = "low";
defparam \RX_DPLL_HOLD[7]~I .oe_register_mode = "none";
defparam \RX_DPLL_HOLD[7]~I .oe_sync_reset = "none";
defparam \RX_DPLL_HOLD[7]~I .operation_mode = "input";
defparam \RX_DPLL_HOLD[7]~I .output_async_reset = "none";
defparam \RX_DPLL_HOLD[7]~I .output_power_up = "low";
defparam \RX_DPLL_HOLD[7]~I .output_register_mode = "none";
defparam \RX_DPLL_HOLD[7]~I .output_sync_reset = "none";
defparam \RX_DPLL_HOLD[7]~I .sim_dqs_delay_increment = 0;
defparam \RX_DPLL_HOLD[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_DPLL_HOLD[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_M23
stratixii_io \RX_DPLL_EN[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\RX_DPLL_EN~combout [7]),
	.regout(),
	.ddioregout(),
	.dqsbusout(),
	.linkout(),
	.padio(RX_DPLL_EN[7]));
// synopsys translate_off
defparam \RX_DPLL_EN[7]~I .ddio_mode = "none";
defparam \RX_DPLL_EN[7]~I .ddioinclk_input = "negated_inclk";
defparam \RX_DPLL_EN[7]~I .dqs_delay_buffer_mode = "none";
defparam \RX_DPLL_EN[7]~I .dqs_out_mode = "none";
defparam \RX_DPLL_EN[7]~I .inclk_input = "normal";
defparam \RX_DPLL_EN[7]~I .input_async_reset = "none";
defparam \RX_DPLL_EN[7]~I .input_power_up = "low";
defparam \RX_DPLL_EN[7]~I .input_register_mode = "none";
defparam \RX_DPLL_EN[7]~I .input_sync_reset = "none";
defparam \RX_DPLL_EN[7]~I .oe_async_reset = "none";
defparam \RX_DPLL_EN[7]~I .oe_power_up = "low";
defparam \RX_DPLL_EN[7]~I .oe_register_mode = "none";
defparam \RX_DPLL_EN[7]~I .oe_sync_reset = "none";
defparam \RX_DPLL_EN[7]~I .operation_mode = "input";
defparam \RX_DPLL_EN[7]~I .output_async_reset = "none";
defparam \RX_DPLL_EN[7]~I .output_power_up = "low";
defparam \RX_DPLL_EN[7]~I .output_register_mode = "none";
defparam \RX_DPLL_EN[7]~I .output_sync_reset = "none";
defparam \RX_DPLL_EN[7]~I .sim_dqs_delay_increment = 0;
defparam \RX_DPLL_EN[7]~I .sim_dqs_intrinsic_delay = 0;
defparam \RX_DPLL_EN[7]~I .sim_dqs_offset_increment = 0;
// synopsys translate_on

// atom is at PIN_M20
stratixii_io \RX_FIFO_RST[7]~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
12345

altlvds_stratixii.vo - 源码说明

本页面展示了「CPLD/FPGA常用模块与综合系统设计实例光盘程序」中的 altlvds_stratixii.vo 源码文件，采用 VO 编程语言编写，共 1,717 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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