altlvds_ex2_msim.do

来自「CPLD/FPGA常用模块与综合系统设计实例光盘程序」· DO 代码 · 共 19 行

vlib work
vmap work work
vlib my_atom
vmap my_atom my_atom
vlog -work work cii_altlvds_extpll.vt cii_altlvds_extpll.vo
vlog -work my_atom cycloneii_atoms.v
vsim -L my_atom -t ps work.cii_altlvds_extpll_vlg_vec_tst
view wave
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*pll_reset
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*ref_clock
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*pll_lock
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*rx_in
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*rx_parallel_out
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*slow_clock
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*tx_out
add wave -hexadecimal /cii_altlvds_extpll_vlg_vec_tst/*tx_parallel_data
run 1us