altlvds_stratixii.vo

CPLD/FPGA常用模块与综合系统设计实例光盘程序

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.2 Internal Build 120 07/26/2007 SJ Full Version"

// DATE "09/04/2007 22:51:14"

// 
// Device: Altera EP2S60F672C3 Package FBGA672
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module altlvds_stratixII (
	PLL_LOCK,
	CLK_IN_500MHZ,
	PLL_ENABLE,
	PLL_ARESET,
	RX_CDA_RST,
	RX_CH_DATA_ALIGN,
	RX_DPLL_EN,
	RX_DPLL_HOLD,
	RX_FIFO_RST,
	RX_IN,
	RX_RESET,
	RX_OUTCLOCK,
	TX_OUTCLOCK,
	TX_CORECLOCK,
	CDA_MAX,
	RX_DPA_LOCKED,
	TX_OUT);
output 	PLL_LOCK;
input 	CLK_IN_500MHZ;
input 	PLL_ENABLE;
input 	PLL_ARESET;
input 	[7:0] RX_CDA_RST;
input 	[7:0] RX_CH_DATA_ALIGN;
input 	[7:0] RX_DPLL_EN;
input 	[7:0] RX_DPLL_HOLD;
input 	[7:0] RX_FIFO_RST;
input 	[7:0] RX_IN;
input 	[7:0] RX_RESET;
output 	RX_OUTCLOCK;
output 	TX_OUTCLOCK;
output 	TX_CORECLOCK;
output 	[7:0] CDA_MAX;
output 	[7:0] RX_DPA_LOCKED;
output 	[7:0] TX_OUT;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri1 devoe;
wire \inst1|altlvds_tx_component|auto_generated|wire_pll_locked ;
wire \inst1|altlvds_tx_component|auto_generated|wire_pll_enable0 ;
wire \inst|altlvds_rx_component|auto_generated|rx_outclock_buf|wire_clkctrl3_outclk ;
wire \inst1|altlvds_tx_component|auto_generated|wire_outclock_tx_dataout ;
wire \PLL_ENABLE~combout ;
wire \PLL_ARESET~combout ;
wire \CLK_IN_500MHZ~combout ;
wire [63:0] \inst|altlvds_rx_component|auto_generated|rxreg ;
wire [7:0] \inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax ;
wire [7:0] \inst|altlvds_rx_component|auto_generated|wire_rx_dpalock ;
wire [5:0] \inst1|altlvds_tx_component|auto_generated|wire_pll_clk ;
wire [1:0] \inst1|altlvds_tx_component|auto_generated|wire_pll_sclkout ;
wire [7:0] \inst1|altlvds_tx_component|auto_generated|wire_tx_dataout ;
wire [7:0] \RX_CDA_RST~combout ;
wire [7:0] \RX_CH_DATA_ALIGN~combout ;
wire [7:0] \RX_DPLL_EN~combout ;
wire [7:0] \RX_DPLL_HOLD~combout ;
wire [7:0] \RX_FIFO_RST~combout ;
wire [7:0] \RX_IN~combout ;
wire [7:0] \RX_RESET~combout ;


stratixii_tx inst1(
	.wire_pll_locked(\inst1|altlvds_tx_component|auto_generated|wire_pll_locked ),
	.wire_pll_enable0(\inst1|altlvds_tx_component|auto_generated|wire_pll_enable0 ),
	.wire_pll_clk_0(\inst1|altlvds_tx_component|auto_generated|wire_pll_clk [0]),
	.wire_pll_sclkout_0(\inst1|altlvds_tx_component|auto_generated|wire_pll_sclkout [0]),
	.wire_clkctrl3_outclk(\inst|altlvds_rx_component|auto_generated|rx_outclock_buf|wire_clkctrl3_outclk ),
	.wire_outclock_tx_dataout(\inst1|altlvds_tx_component|auto_generated|wire_outclock_tx_dataout ),
	.wire_tx_dataout_7(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [7]),
	.wire_tx_dataout_6(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [6]),
	.wire_tx_dataout_5(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [5]),
	.wire_tx_dataout_4(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [4]),
	.wire_tx_dataout_3(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [3]),
	.wire_tx_dataout_2(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [2]),
	.wire_tx_dataout_1(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [1]),
	.wire_tx_dataout_0(\inst1|altlvds_tx_component|auto_generated|wire_tx_dataout [0]),
	.rxreg_56(\inst|altlvds_rx_component|auto_generated|rxreg [56]),
	.rxreg_57(\inst|altlvds_rx_component|auto_generated|rxreg [57]),
	.rxreg_58(\inst|altlvds_rx_component|auto_generated|rxreg [58]),
	.rxreg_59(\inst|altlvds_rx_component|auto_generated|rxreg [59]),
	.rxreg_60(\inst|altlvds_rx_component|auto_generated|rxreg [60]),
	.rxreg_61(\inst|altlvds_rx_component|auto_generated|rxreg [61]),
	.rxreg_62(\inst|altlvds_rx_component|auto_generated|rxreg [62]),
	.rxreg_63(\inst|altlvds_rx_component|auto_generated|rxreg [63]),
	.rxreg_48(\inst|altlvds_rx_component|auto_generated|rxreg [48]),
	.rxreg_49(\inst|altlvds_rx_component|auto_generated|rxreg [49]),
	.rxreg_50(\inst|altlvds_rx_component|auto_generated|rxreg [50]),
	.rxreg_51(\inst|altlvds_rx_component|auto_generated|rxreg [51]),
	.rxreg_52(\inst|altlvds_rx_component|auto_generated|rxreg [52]),
	.rxreg_53(\inst|altlvds_rx_component|auto_generated|rxreg [53]),
	.rxreg_54(\inst|altlvds_rx_component|auto_generated|rxreg [54]),
	.rxreg_55(\inst|altlvds_rx_component|auto_generated|rxreg [55]),
	.rxreg_40(\inst|altlvds_rx_component|auto_generated|rxreg [40]),
	.rxreg_41(\inst|altlvds_rx_component|auto_generated|rxreg [41]),
	.rxreg_42(\inst|altlvds_rx_component|auto_generated|rxreg [42]),
	.rxreg_43(\inst|altlvds_rx_component|auto_generated|rxreg [43]),
	.rxreg_44(\inst|altlvds_rx_component|auto_generated|rxreg [44]),
	.rxreg_45(\inst|altlvds_rx_component|auto_generated|rxreg [45]),
	.rxreg_46(\inst|altlvds_rx_component|auto_generated|rxreg [46]),
	.rxreg_47(\inst|altlvds_rx_component|auto_generated|rxreg [47]),
	.rxreg_32(\inst|altlvds_rx_component|auto_generated|rxreg [32]),
	.rxreg_33(\inst|altlvds_rx_component|auto_generated|rxreg [33]),
	.rxreg_34(\inst|altlvds_rx_component|auto_generated|rxreg [34]),
	.rxreg_35(\inst|altlvds_rx_component|auto_generated|rxreg [35]),
	.rxreg_36(\inst|altlvds_rx_component|auto_generated|rxreg [36]),
	.rxreg_37(\inst|altlvds_rx_component|auto_generated|rxreg [37]),
	.rxreg_38(\inst|altlvds_rx_component|auto_generated|rxreg [38]),
	.rxreg_39(\inst|altlvds_rx_component|auto_generated|rxreg [39]),
	.rxreg_24(\inst|altlvds_rx_component|auto_generated|rxreg [24]),
	.rxreg_25(\inst|altlvds_rx_component|auto_generated|rxreg [25]),
	.rxreg_26(\inst|altlvds_rx_component|auto_generated|rxreg [26]),
	.rxreg_27(\inst|altlvds_rx_component|auto_generated|rxreg [27]),
	.rxreg_28(\inst|altlvds_rx_component|auto_generated|rxreg [28]),
	.rxreg_29(\inst|altlvds_rx_component|auto_generated|rxreg [29]),
	.rxreg_30(\inst|altlvds_rx_component|auto_generated|rxreg [30]),
	.rxreg_31(\inst|altlvds_rx_component|auto_generated|rxreg [31]),
	.rxreg_16(\inst|altlvds_rx_component|auto_generated|rxreg [16]),
	.rxreg_17(\inst|altlvds_rx_component|auto_generated|rxreg [17]),
	.rxreg_18(\inst|altlvds_rx_component|auto_generated|rxreg [18]),
	.rxreg_19(\inst|altlvds_rx_component|auto_generated|rxreg [19]),
	.rxreg_20(\inst|altlvds_rx_component|auto_generated|rxreg [20]),
	.rxreg_21(\inst|altlvds_rx_component|auto_generated|rxreg [21]),
	.rxreg_22(\inst|altlvds_rx_component|auto_generated|rxreg [22]),
	.rxreg_23(\inst|altlvds_rx_component|auto_generated|rxreg [23]),
	.rxreg_8(\inst|altlvds_rx_component|auto_generated|rxreg [8]),
	.rxreg_9(\inst|altlvds_rx_component|auto_generated|rxreg [9]),
	.rxreg_10(\inst|altlvds_rx_component|auto_generated|rxreg [10]),
	.rxreg_11(\inst|altlvds_rx_component|auto_generated|rxreg [11]),
	.rxreg_12(\inst|altlvds_rx_component|auto_generated|rxreg [12]),
	.rxreg_13(\inst|altlvds_rx_component|auto_generated|rxreg [13]),
	.rxreg_14(\inst|altlvds_rx_component|auto_generated|rxreg [14]),
	.rxreg_15(\inst|altlvds_rx_component|auto_generated|rxreg [15]),
	.rxreg_0(\inst|altlvds_rx_component|auto_generated|rxreg [0]),
	.rxreg_1(\inst|altlvds_rx_component|auto_generated|rxreg [1]),
	.rxreg_2(\inst|altlvds_rx_component|auto_generated|rxreg [2]),
	.rxreg_3(\inst|altlvds_rx_component|auto_generated|rxreg [3]),
	.rxreg_4(\inst|altlvds_rx_component|auto_generated|rxreg [4]),
	.rxreg_5(\inst|altlvds_rx_component|auto_generated|rxreg [5]),
	.rxreg_6(\inst|altlvds_rx_component|auto_generated|rxreg [6]),
	.rxreg_7(\inst|altlvds_rx_component|auto_generated|rxreg [7]),
	.PLL_ENABLE(\PLL_ENABLE~combout ),
	.PLL_ARESET(\PLL_ARESET~combout ),
	.CLK_IN_500MHZ(\CLK_IN_500MHZ~combout ),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

stratixii_rx inst(
	.wire_pll_enable0(\inst1|altlvds_tx_component|auto_generated|wire_pll_enable0 ),
	.wire_pll_clk_0(\inst1|altlvds_tx_component|auto_generated|wire_pll_clk [0]),
	.wire_pll_sclkout_0(\inst1|altlvds_tx_component|auto_generated|wire_pll_sclkout [0]),
	.rx_outclock(\inst|altlvds_rx_component|auto_generated|rx_outclock_buf|wire_clkctrl3_outclk ),
	.wire_rx_dpalock_7(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [7]),
	.wire_rx_bitslipmax_7(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [7]),
	.wire_rx_dpalock_6(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [6]),
	.wire_rx_bitslipmax_6(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [6]),
	.wire_rx_dpalock_5(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [5]),
	.wire_rx_bitslipmax_5(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [5]),
	.wire_rx_dpalock_4(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [4]),
	.wire_rx_bitslipmax_4(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [4]),
	.wire_rx_dpalock_3(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [3]),
	.wire_rx_bitslipmax_3(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [3]),
	.wire_rx_dpalock_2(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [2]),
	.wire_rx_bitslipmax_2(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [2]),
	.wire_rx_dpalock_1(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [1]),
	.wire_rx_bitslipmax_1(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [1]),
	.wire_rx_dpalock_0(\inst|altlvds_rx_component|auto_generated|wire_rx_dpalock [0]),
	.wire_rx_bitslipmax_0(\inst|altlvds_rx_component|auto_generated|wire_rx_bitslipmax [0]),
	.rxreg_56(\inst|altlvds_rx_component|auto_generated|rxreg [56]),
	.rxreg_57(\inst|altlvds_rx_component|auto_generated|rxreg [57]),
	.rxreg_58(\inst|altlvds_rx_component|auto_generated|rxreg [58]),
	.rxreg_59(\inst|altlvds_rx_component|auto_generated|rxreg [59]),
	.rxreg_60(\inst|altlvds_rx_component|auto_generated|rxreg [60]),
	.rxreg_61(\inst|altlvds_rx_component|auto_generated|rxreg [61]),
	.rxreg_62(\inst|altlvds_rx_component|auto_generated|rxreg [62]),
	.rxreg_63(\inst|altlvds_rx_component|auto_generated|rxreg [63]),
	.rxreg_48(\inst|altlvds_rx_component|auto_generated|rxreg [48]),
	.rxreg_49(\inst|altlvds_rx_component|auto_generated|rxreg [49]),
	.rxreg_50(\inst|altlvds_rx_component|auto_generated|rxreg [50]),
	.rxreg_51(\inst|altlvds_rx_component|auto_generated|rxreg [51]),
	.rxreg_52(\inst|altlvds_rx_component|auto_generated|rxreg [52]),
	.rxreg_53(\inst|altlvds_rx_component|auto_generated|rxreg [53]),
	.rxreg_54(\inst|altlvds_rx_component|auto_generated|rxreg [54]),
	.rxreg_55(\inst|altlvds_rx_component|auto_generated|rxreg [55]),
	.rxreg_40(\inst|altlvds_rx_component|auto_generated|rxreg [40]),
	.rxreg_41(\inst|altlvds_rx_component|auto_generated|rxreg [41]),
	.rxreg_42(\inst|altlvds_rx_component|auto_generated|rxreg [42]),
	.rxreg_43(\inst|altlvds_rx_component|auto_generated|rxreg [43]),
	.rxreg_44(\inst|altlvds_rx_component|auto_generated|rxreg [44]),
	.rxreg_45(\inst|altlvds_rx_component|auto_generated|rxreg [45]),
	.rxreg_46(\inst|altlvds_rx_component|auto_generated|rxreg [46]),
	.rxreg_47(\inst|altlvds_rx_component|auto_generated|rxreg [47]),
	.rxreg_32(\inst|altlvds_rx_component|auto_generated|rxreg [32]),
	.rxreg_33(\inst|altlvds_rx_component|auto_generated|rxreg [33]),
	.rxreg_34(\inst|altlvds_rx_component|auto_generated|rxreg [34]),
	.rxreg_35(\inst|altlvds_rx_component|auto_generated|rxreg [35]),
	.rxreg_36(\inst|altlvds_rx_component|auto_generated|rxreg [36]),
	.rxreg_37(\inst|altlvds_rx_component|auto_generated|rxreg [37]),
	.rxreg_38(\inst|altlvds_rx_component|auto_generated|rxreg [38]),
	.rxreg_39(\inst|altlvds_rx_component|auto_generated|rxreg [39]),
	.rxreg_24(\inst|altlvds_rx_component|auto_generated|rxreg [24]),
	.rxreg_25(\inst|altlvds_rx_component|auto_generated|rxreg [25]),
	.rxreg_26(\inst|altlvds_rx_component|auto_generated|rxreg [26]),
	.rxreg_27(\inst|altlvds_rx_component|auto_generated|rxreg [27]),
	.rxreg_28(\inst|altlvds_rx_component|auto_generated|rxreg [28]),
	.rxreg_29(\inst|altlvds_rx_component|auto_generated|rxreg [29]),
	.rxreg_30(\inst|altlvds_rx_component|auto_generated|rxreg [30]),
	.rxreg_31(\inst|altlvds_rx_component|auto_generated|rxreg [31]),
	.rxreg_16(\inst|altlvds_rx_component|auto_generated|rxreg [16]),
	.rxreg_17(\inst|altlvds_rx_component|auto_generated|rxreg [17]),
	.rxreg_18(\inst|altlvds_rx_component|auto_generated|rxreg [18]),
	.rxreg_19(\inst|altlvds_rx_component|auto_generated|rxreg [19]),
	.rxreg_20(\inst|altlvds_rx_component|auto_generated|rxreg [20]),
	.rxreg_21(\inst|altlvds_rx_component|auto_generated|rxreg [21]),
	.rxreg_22(\inst|altlvds_rx_component|auto_generated|rxreg [22]),
	.rxreg_23(\inst|altlvds_rx_component|auto_generated|rxreg [23]),
	.rxreg_8(\inst|altlvds_rx_component|auto_generated|rxreg [8]),
	.rxreg_9(\inst|altlvds_rx_component|auto_generated|rxreg [9]),
	.rxreg_10(\inst|altlvds_rx_component|auto_generated|rxreg [10]),
	.rxreg_11(\inst|altlvds_rx_component|auto_generated|rxreg [11]),
	.rxreg_12(\inst|altlvds_rx_component|auto_generated|rxreg [12]),
	.rxreg_13(\inst|altlvds_rx_component|auto_generated|rxreg [13]),
	.rxreg_14(\inst|altlvds_rx_component|auto_generated|rxreg [14]),
	.rxreg_15(\inst|altlvds_rx_component|auto_generated|rxreg [15]),
	.rxreg_0(\inst|altlvds_rx_component|auto_generated|rxreg [0]),
	.rxreg_1(\inst|altlvds_rx_component|auto_generated|rxreg [1]),
	.rxreg_2(\inst|altlvds_rx_component|auto_generated|rxreg [2]),
	.rxreg_3(\inst|altlvds_rx_component|auto_generated|rxreg [3]),
	.rxreg_4(\inst|altlvds_rx_component|auto_generated|rxreg [4]),
	.rxreg_5(\inst|altlvds_rx_component|auto_generated|rxreg [5]),
	.rxreg_6(\inst|altlvds_rx_component|auto_generated|rxreg [6]),
	.rxreg_7(\inst|altlvds_rx_component|auto_generated|rxreg [7]),
	.RX_IN_7(\RX_IN~combout [7]),
	.RX_RESET_7(\RX_RESET~combout [7]),
	.RX_DPLL_HOLD_7(\RX_DPLL_HOLD~combout [7]),
	.RX_DPLL_EN_7(\RX_DPLL_EN~combout [7]),
	.RX_FIFO_RST_7(\RX_FIFO_RST~combout [7]),
	.RX_CH_DATA_ALIGN_7(\RX_CH_DATA_ALIGN~combout [7]),
	.RX_CDA_RST_7(\RX_CDA_RST~combout [7]),
	.RX_IN_6(\RX_IN~combout [6]),
	.RX_RESET_6(\RX_RESET~combout [6]),
	.RX_DPLL_HOLD_6(\RX_DPLL_HOLD~combout [6]),
	.RX_DPLL_EN_6(\RX_DPLL_EN~combout [6]),
	.RX_FIFO_RST_6(\RX_FIFO_RST~combout [6]),
	.RX_CH_DATA_ALIGN_6(\RX_CH_DATA_ALIGN~combout [6]),
	.RX_CDA_RST_6(\RX_CDA_RST~combout [6]),
	.RX_IN_5(\RX_IN~combout [5]),
	.RX_RESET_5(\RX_RESET~combout [5]),
	.RX_DPLL_HOLD_5(\RX_DPLL_HOLD~combout [5]),
	.RX_DPLL_EN_5(\RX_DPLL_EN~combout [5]),
	.RX_FIFO_RST_5(\RX_FIFO_RST~combout [5]),
	.RX_CH_DATA_ALIGN_5(\RX_CH_DATA_ALIGN~combout [5]),
	.RX_CDA_RST_5(\RX_CDA_RST~combout [5]),
	.RX_IN_4(\RX_IN~combout [4]),
	.RX_RESET_4(\RX_RESET~combout [4]),
	.RX_DPLL_HOLD_4(\RX_DPLL_HOLD~combout [4]),
	.RX_DPLL_EN_4(\RX_DPLL_EN~combout [4]),
	.RX_FIFO_RST_4(\RX_FIFO_RST~combout [4]),
	.RX_CH_DATA_ALIGN_4(\RX_CH_DATA_ALIGN~combout [4]),
	.RX_CDA_RST_4(\RX_CDA_RST~combout [4]),
	.RX_IN_3(\RX_IN~combout [3]),
	.RX_RESET_3(\RX_RESET~combout [3]),
	.RX_DPLL_HOLD_3(\RX_DPLL_HOLD~combout [3]),
	.RX_DPLL_EN_3(\RX_DPLL_EN~combout [3]),
	.RX_FIFO_RST_3(\RX_FIFO_RST~combout [3]),
	.RX_CH_DATA_ALIGN_3(\RX_CH_DATA_ALIGN~combout [3]),
	.RX_CDA_RST_3(\RX_CDA_RST~combout [3]),
	.RX_IN_2(\RX_IN~combout [2]),
	.RX_RESET_2(\RX_RESET~combout [2]),
	.RX_DPLL_HOLD_2(\RX_DPLL_HOLD~combout [2]),
	.RX_DPLL_EN_2(\RX_DPLL_EN~combout [2]),
	.RX_FIFO_RST_2(\RX_FIFO_RST~combout [2]),
	.RX_CH_DATA_ALIGN_2(\RX_CH_DATA_ALIGN~combout [2]),
	.RX_CDA_RST_2(\RX_CDA_RST~combout [2]),
	.RX_IN_1(\RX_IN~combout [1]),
	.RX_RESET_1(\RX_RESET~combout [1]),
	.RX_DPLL_HOLD_1(\RX_DPLL_HOLD~combout [1]),
	.RX_DPLL_EN_1(\RX_DPLL_EN~combout [1]),
	.RX_FIFO_RST_1(\RX_FIFO_RST~combout [1]),
	.RX_CH_DATA_ALIGN_1(\RX_CH_DATA_ALIGN~combout [1]),
	.RX_CDA_RST_1(\RX_CDA_RST~combout [1]),
	.RX_IN_0(\RX_IN~combout [0]),
	.RX_RESET_0(\RX_RESET~combout [0]),
	.RX_DPLL_HOLD_0(\RX_DPLL_HOLD~combout [0]),
	.RX_DPLL_EN_0(\RX_DPLL_EN~combout [0]),
	.RX_FIFO_RST_0(\RX_FIFO_RST~combout [0]),
	.RX_CH_DATA_ALIGN_0(\RX_CH_DATA_ALIGN~combout [0]),
	.RX_CDA_RST_0(\RX_CDA_RST~combout [0]),
	.devpor(devpor),
	.devclrn(devclrn),
	.devoe(devoe));

// atom is at PIN_AB6
stratixii_io \PLL_ENABLE~I (
	.datain(gnd),
	.ddiodatain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.ddioinclk(gnd),
	.dqsupdateen(vcc),
	.linkin(gnd),
	.delayctrlin(6'b000000),
	.offsetctrlin(6'b000000),
	.terminationcontrol(14'b00000000000000),
	.devclrn(devclrn),
	.devpor(devpor),