alu3.v

用verilog语言编写

module alu3(out,data1,data2,opcode,clk);
output[7:0] out;
input[7:0] data1,data2;
input[2:0] opcode;
input clk;
reg[7:0] out;
parameter ADD = 3'd1,
	 	  SUB = 3'd2,
		  AND = 3'd3,
	 	  OR  = 3'd4,
	  	  NOT = 3'd5;
always@(posedge clk)
begin
case(opcode)
ADD: out<=data1+data2;
SUB: out<=data1+(~data2+1);
AND: out<=data1&data2;
 OR: out<=data1|data2;
NOT: out<=~data1;
default: out<=8'bX;
endcase
end
endmodule