test1.v

来自「VHDL实现倍频--偶数倍 分频电路 --分频倍数=2（n+1）」· Verilog 代码 · 共 33 行

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

module test1(
	pin_name,
	pin_name1,
	pin_name2
);

input	pin_name;
input	pin_name1;
output	pin_name2;





assign	pin_name2 = pin_name & pin_name1;


endmodule