clock_v.vhd

个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真

library IEEE;
use IEEE.std_logic_1164.all;
package clock_v is
COMPONENT second
	PORT(
         CLk,reset,setmin : IN  STD_LOGIC;
		 daout      : OUT STD_LOGIC_VECTOR(6 downto 0);
		 enmin      : OUT STD_LOGIC                   
        );
END COMPONENT;

COMPONENT minute 
	PORT(
         CLk,reset,sethour : IN  STD_LOGIC;
		 daout      : OUT STD_LOGIC_VECTOR(6 downto 0);
		 enhour      : OUT STD_LOGIC                   
        );
END COMPONENT;
component hour
	PORT(
         clk,reset		: IN  STD_LOGIC;
		 daout          : OUT STD_LOGIC_VECTOR(5 downto 0)                 
        );
end component;
component seltime_dc
PORT(
         clk,reset  : IN  STD_LOGIC;
         sec,min   :in  std_logic_vector(6 downto 0);
         hour      :in std_logic_vector(5 downto 0);
         s        :out std_logic_vector( 6 downto 0);
	    sel       :out std_logic_vector(2 downto 0)                
        );
end component;
component alert 
	PORT(
         clk	: IN  STD_LOGIC;
         dain  : in std_logic_vector(6 downto 0);
		 lamp         : OUT STD_LOGIC_VECTOR(2 downto 0);
         speak  : out std_logic                 
        );
end component;
component clock_con
PORT(
         clk,set,model	: IN  STD_LOGIC;
         setmin,sethour: OUT STD_LOGIC                
        );
end component;

end clock_v;