alert.rpt

来自「个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真」· RPT 代码 · 共 426 行 · 第 1/2 页

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              k:\timevhd\alert.rpt
alert

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (40)    18    B       TFFE   +  t        0      0   0    7    1    3    0  lamp_b1 (:16)
 (41)    17    B       TFFE   +  t        0      0   0    7    0    3    1  lamp_b0 (:17)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              k:\timevhd\alert.rpt
alert

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                     Logic cells placed in LAB 'B'
        +----------- LC22 lamp0
        | +--------- LC23 lamp1
        | | +------- LC21 lamp2
        | | | +----- LC19 speak
        | | | | +--- LC18 lamp_b1
        | | | | | +- LC17 lamp_b0
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'B'
LC      | | | | | | | A B |     Logic cells that feed LAB 'B':
LC18 -> * * * - * - | - * | <-- lamp_b1
LC17 -> * * * - * * | - * | <-- lamp_b0

Pin
43   -> - - - - - - | - - | <-- clk
8    -> - - - * * * | - * | <-- dain0
9    -> - - - * * * | - * | <-- dain1
12   -> - - - * * * | - * | <-- dain2
11   -> - - - * * * | - * | <-- dain3
6    -> - - - * * * | - * | <-- dain4
5    -> - - - * * * | - * | <-- dain5
4    -> - - - * * * | - * | <-- dain6


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              k:\timevhd\alert.rpt
alert

** EQUATIONS **

clk      : INPUT;
dain0    : INPUT;
dain1    : INPUT;
dain2    : INPUT;
dain3    : INPUT;
dain4    : INPUT;
dain5    : INPUT;
dain6    : INPUT;

-- Node name is ':17' = 'lamp_b0' 
-- Equation name is 'lamp_b0', location is LC017, type is buried.
lamp_b0  = TFFE( _EQ001, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ001 = !dain0 & !dain1 & !dain2 & !dain3 & !dain4 & !dain5 & !dain6;

-- Node name is ':16' = 'lamp_b1' 
-- Equation name is 'lamp_b1', location is LC018, type is buried.
lamp_b1  = TFFE( _EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !dain0 & !dain1 & !dain2 & !dain3 & !dain4 & !dain5 & !dain6 & 
              lamp_b0;

-- Node name is 'lamp0' 
-- Equation name is 'lamp0', location is LC022, type is output.
 lamp0   = LCELL( _EQ003 $  lamp_b0);
  _EQ003 =  lamp_b0 &  lamp_b1;

-- Node name is 'lamp1' 
-- Equation name is 'lamp1', location is LC023, type is output.
 lamp1   = LCELL( _EQ004 $  lamp_b1);
  _EQ004 =  lamp_b0 &  lamp_b1;

-- Node name is 'lamp2' 
-- Equation name is 'lamp2', location is LC021, type is output.
 lamp2   = LCELL( _EQ005 $  lamp_b0);
  _EQ005 =  lamp_b0 & !lamp_b1;

-- Node name is 'speak' = 'speak_b' 
-- Equation name is 'speak', location is LC019, type is output.
 speak   = TFFE( _EQ006, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 = !dain0 & !dain1 & !dain2 & !dain3 & !dain4 & !dain5 & !dain6;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       k:\timevhd\alert.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:04
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,713K