clock_con.vhd

个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY clock_con IS
	PORT(
         clk,set,model	: IN  STD_LOGIC;
         setmin,sethour: OUT STD_LOGIC                
        );
END clock_con;

ARCHITECTURE a OF clock_con IS
 type  fsm  IS (st0, st1, st2); 
 signal   temp :fsm;
 BEGIN
reg:  PROCESS (clk)
 begin
 if clk'event and clk='1' then
  CASE temp IS           
        WHEN st0 => IF model= '0' THEN  temp <= st1; END IF;
        WHEN st1 => IF model= '0' THEN  temp <= st2; END IF;
        WHEN st2 => IF model= '0' THEN  temp <= st0; END IF;
        WHEN OTHERS => temp <= st0; 
     END CASE ;
   END IF;
     end process reg;
COM1: PROCESS(temp,set)
 BEGIN 
   CASE temp IS           
     WHEN st0 => setmin <= '1'; sethour<='1';
     WHEN st1 => IF set = '0' THEN setmin <= '0'; sethour<='1';

                  ELSE setmin <= '1'; sethour<='1';
                  END IF ; 
     when st2=> if set='0' then setmin <= '1'; sethour<='0';
                  else setmin <= '1'; sethour<='1';
                  end if ;
  WHEN OTHERS => setmin <= '1'; sethour<='1';                
  END CASE ;
END PROCESS COM1 ;
                  
END a;