alert.vhd

来自「个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真」· VHDL 代码 · 共 48 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY alert IS
	PORT(
         clk	: IN  STD_LOGIC;
         dain  : in std_logic_vector(6 downto 0);
		 lamp         : OUT STD_LOGIC_VECTOR(2 downto 0);
         speak  : out std_logic                 
        );
END alert;

ARCHITECTURE a OF alert IS
 signal   temp :std_logic_vector(1 downto 0);
 BEGIN
  PROCESS (clk,dain)
            VARIABLE speak_b         : STD_LOGIC;
		    VARIABLE lamp_b         : STD_LOGIC_VECTOR(2 downto 0);
      BEGIN
     if clk'event and clk='1' then
       if dain="0000000" then 
        speak_b:= not speak_b;
        lamp_b:=lamp_b+1;
				elsif dain="0000001" then 
        		speak_b:= '0';
       end if ;
    end if ;
     speak<=speak_b;
     temp<=lamp_b;
	   END PROCESS;
  process(temp)
  begin
  CASE temp IS
  	WHEN "00" =>
  	   lamp<="000";
  	WHEN "01" =>
  	     lamp<="001";
    WHEN "10" =>
  	   lamp<="010";
  	WHEN "11" =>
  	     lamp<="100";
  	WHEN OTHERS =>
  	    lamp<="000";
  END CASE;
end process;
  
END a;