hour.rpt

个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真

r = Fitter-inserted logic cell


Device-Specific Information:                               k:\timevhd\hour.rpt
hour

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (33)    24    B       SOFT      t        0      0   0    0    2    1    0  |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node1
 (38)    20    B       SOFT      t        0      0   0    0    3    1    0  |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2
 (32)    25    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               k:\timevhd\hour.rpt
hour

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                           Logic cells placed in LAB 'B'
        +----------------- LC19 daout0
        | +--------------- LC23 daout1
        | | +------------- LC21 daout2
        | | | +----------- LC18 daout3
        | | | | +--------- LC17 daout4
        | | | | | +------- LC22 daout5
        | | | | | | +----- LC24 |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node1
        | | | | | | | +--- LC20 |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2
        | | | | | | | | +- LC25 |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node3
        | | | | | | | | | 
        | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC19 -> * * * * * * * * * | - * | <-- daout0
LC23 -> - * * * * * * * * | - * | <-- daout1
LC21 -> - * * * * * - * * | - * | <-- daout2
LC18 -> - * * * * * - - * | - * | <-- daout3
LC17 -> - * * * * * - - - | - * | <-- daout4
LC22 -> - * * * - * - - - | - * | <-- daout5
LC24 -> - * - - - - - - - | - * | <-- |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node1
LC20 -> - - * - - - - - - | - * | <-- |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - * - - - - - | - * | <-- |LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node3

Pin
43   -> - - - - - - - - - | - - | <-- clk
1    -> - - - - - - - - - | - - | <-- reset


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               k:\timevhd\hour.rpt
hour

** EQUATIONS **

clk      : INPUT;
reset    : INPUT;

-- Node name is 'daout0' = 'tmpa0~123' 
-- Equation name is 'daout0', location is LC019, type is output.
 daout0  = TFFE( VCC, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);

-- Node name is 'daout1' = 'tmpa1~123' 
-- Equation name is 'daout1', location is LC023, type is output.
 daout1  = DFFE( _EQ001 $  _LC024, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ001 =  daout0 &  daout1 & !daout2 & !daout3 & !daout4 &  daout5 & 
              _LC024
         #  daout0 & !daout1 & !daout2 &  daout3 &  _LC024;

-- Node name is 'daout2' = 'tmpa2~123' 
-- Equation name is 'daout2', location is LC021, type is output.
 daout2  = DFFE( _EQ002 $  _LC020, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ002 =  daout0 &  daout1 & !daout2 & !daout3 & !daout4 &  daout5 & 
              _LC020
         #  daout0 & !daout1 & !daout2 &  daout3 &  _LC020;

-- Node name is 'daout3' = 'tmpa3~123' 
-- Equation name is 'daout3', location is LC018, type is output.
 daout3  = DFFE( _EQ003 $  _LC025, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ003 =  daout0 &  daout1 & !daout2 & !daout3 & !daout4 &  daout5 & 
              _LC025
         #  daout0 & !daout1 & !daout2 &  daout3 &  _LC025;

-- Node name is 'daout4' = 'tmpb0~121' 
-- Equation name is 'daout4', location is LC017, type is output.
 daout4  = TFFE( _EQ004, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ004 =  daout0 & !daout1 & !daout2 &  daout3;

-- Node name is 'daout5' = 'tmpb1~121' 
-- Equation name is 'daout5', location is LC022, type is output.
 daout5  = TFFE( _EQ005, GLOBAL( clk), GLOBAL( reset),  VCC,  VCC);
  _EQ005 =  daout0 &  daout1 & !daout2 & !daout3 & !daout4 &  daout5
         #  daout0 & !daout1 & !daout2 &  daout3 &  daout4;

-- Node name is '|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( daout1 $  daout0);

-- Node name is '|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( daout2 $  _EQ006);
  _EQ006 =  daout0 &  daout1;

-- Node name is '|LPM_ADD_SUB:92|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( daout3 $  _EQ007);
  _EQ007 =  daout0 &  daout1 &  daout2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        k:\timevhd\hour.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:03
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,423K