clock_top.vhd

个人设计的基于VHDL的数字电子日历 在MAX+PLUSH软件平台上编译、仿真

LIBRARY ieee; 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE Work.clock_v.all;
ENTITY clock_top IS
	PORT(
         clk,reset,set,model,clkdsp		: IN  STD_LOGIC;
		 daout          : OUT STD_LOGIC_VECTOR(6 downto 0);
         speak,enhour,setlp1,setlp2 :out std_logic;
         lamp,sel      :out std_logic_vector(2 downto 0)                
        );
END clock_top;

ARCHITECTURE a OF clock_top IS
SIGNAL sda,mda  : std_logic_vector( 6 downto 0);
SIGNAL ha  : std_logic_vector( 5 downto 0);
SIGNAL enmin_b,enhour_b,setmin_b,sethour_b  : std_logic;
 BEGIN
setlp1<=setmin_b;
setlp2<=sethour_b;
ic0: clock_con
     port map(clk=>clk,set=>set,model=>model,setmin=>setmin_b,sethour=>sethour_b);
ic1: second
	PORT MAP (clk => clk, reset => reset,setmin=>setmin_b,daout=>sda,enmin=>enmin_b);
ic2:minute
    port map (clk=>enmin_b,reset=>reset,sethour=>sethour_b,enhour=>enhour_b,daout=>mda);
ic3:hour
    port map (clk=>enhour_b,reset=>reset,daout=>ha);
ic4: seltime_dc
    port map (clk=>clkdsp,reset=>reset,sec=>sda,min=>mda,hour=>ha,s=>daout,sel=>sel);
ic5:alert
   port map (clk=>clk,dain=>mda,speak=>speak,lamp=>lamp);
enhour<=enhour_b;
--en<=enmin_b and enhour_b;
end a;