fen_pin_10_1.hier_info

来自「利用verilog语言」· HIER_INFO 代码 · 共 49 行

|fen_pin_10_1
out <= inst6.DB_MAX_OUTPUT_PORT_TYPE
in_28 => enable:inst3.clk
in_28 => counter11:inst5.clk11
in_28 => counter10:inst1.clk10
out10 <= counter10:inst1.out10
out11 <= counter11:inst5.out11


|fen_pin_10_1|counter11:inst5
out11 <= out11~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable11 => out11~0.OUTPUTSELECT
enable11 => cout11~4.OUTPUTSELECT
enable11 => cout11~5.OUTPUTSELECT
enable11 => cout11~6.OUTPUTSELECT
enable11 => cout11~7.OUTPUTSELECT
clk11 => cout11[3].CLK
clk11 => cout11[2].CLK
clk11 => cout11[1].CLK
clk11 => cout11[0].CLK
clk11 => out11~reg0.CLK


|fen_pin_10_1|enable:inst3
outin <= always1~0.DB_MAX_OUTPUT_PORT_TYPE
clk => counter101[5].CLK
clk => counter101[4].CLK
clk => counter101[3].CLK
clk => counter101[2].CLK
clk => counter101[1].CLK
clk => counter101[0].CLK
clk => counter101[6].CLK


|fen_pin_10_1|counter10:inst1
out10 <= out10~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable10 => out10~0.OUTPUTSELECT
enable10 => cout~4.OUTPUTSELECT
enable10 => cout~5.OUTPUTSELECT
enable10 => cout~6.OUTPUTSELECT
enable10 => cout~7.OUTPUTSELECT
clk10 => cout[3].CLK
clk10 => cout[2].CLK
clk10 => cout[1].CLK
clk10 => cout[0].CLK
clk10 => out10~reg0.CLK