fen_pin_10_1.fnsim.qmsg

来自「利用verilog语言」· QMSG 代码 · 共 13 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 27 09:42:30 2007 " "Info: Processing started: Thu Dec 27 09:42:30 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter11.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file counter11.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter11 " "Info: Found entity 1: counter11" {  } { { "counter11.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/counter11.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "couter10.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file couter10.v" { { "Info" "ISGN_ENTITY_NAME" "1 counter10 " "Info: Found entity 1: counter10" {  } { { "couter10.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/couter10.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "enable.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file enable.v" { { "Info" "ISGN_ENTITY_NAME" "1 enable " "Info: Found entity 1: enable" {  } { { "enable.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/enable.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fen_pin_10_1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fen_pin_10_1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fen_pin_10_1 " "Info: Found entity 1: fen_pin_10_1" {  } { { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "fen_pin_10_1 " "Info: Elaborating entity \"fen_pin_10_1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter11 counter11:inst5 " "Info: Elaborating entity \"counter11\" for hierarchy \"counter11:inst5\"" {  } { { "fen_pin_10_1.bdf" "inst5" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 184 464 592 280 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "enable enable:inst3 " "Info: Elaborating entity \"enable\" for hierarchy \"enable:inst3\"" {  } { { "fen_pin_10_1.bdf" "inst3" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 256 216 312 352 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter10 counter10:inst1 " "Info: Elaborating entity \"counter10\" for hierarchy \"counter10:inst1\"" {  } { { "fen_pin_10_1.bdf" "inst1" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 64 464 592 160 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 0 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 09:42:31 2007 " "Info: Processing ended: Thu Dec 27 09:42:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}