fen_pin_10_1.tan.qmsg

利用verilog语言

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "in_28 register enable:inst3\|counter101\[6\] register counter10:inst1\|cout\[0\] 262.26 MHz 3.813 ns Internal " "Info: Clock \"in_28\" has Internal fmax of 262.26 MHz between source register \"enable:inst3\|counter101\[6\]\" and destination register \"counter10:inst1\|cout\[0\]\" (period= 3.813 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.547 ns + Longest register register " "Info: + Longest register to register delay is 3.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns enable:inst3\|counter101\[6\] 1 REG LCFF_X17_Y30_N11 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y30_N11; Fanout = 9; REG Node = 'enable:inst3\|counter101\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { enable:inst3|counter101[6] } "NODE_NAME" } } { "enable.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/enable.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.512 ns) + CELL(0.651 ns) 1.163 ns enable:inst3\|always1~120 2 COMB LCCOMB_X17_Y30_N22 1 " "Info: 2: + IC(0.512 ns) + CELL(0.651 ns) = 1.163 ns; Loc. = LCCOMB_X17_Y30_N22; Fanout = 1; COMB Node = 'enable:inst3\|always1~120'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.163 ns" { enable:inst3|counter101[6] enable:inst3|always1~120 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.624 ns) 2.173 ns enable:inst3\|always1~121 3 COMB LCCOMB_X17_Y30_N26 6 " "Info: 3: + IC(0.386 ns) + CELL(0.624 ns) = 2.173 ns; Loc. = LCCOMB_X17_Y30_N26; Fanout = 6; COMB Node = 'enable:inst3\|always1~121'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.010 ns" { enable:inst3|always1~120 enable:inst3|always1~121 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.732 ns) + CELL(0.534 ns) 3.439 ns counter10:inst1\|cout~161 4 COMB LCCOMB_X16_Y30_N22 1 " "Info: 4: + IC(0.732 ns) + CELL(0.534 ns) = 3.439 ns; Loc. = LCCOMB_X16_Y30_N22; Fanout = 1; COMB Node = 'counter10:inst1\|cout~161'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.266 ns" { enable:inst3|always1~121 counter10:inst1|cout~161 } "NODE_NAME" } } { "couter10.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/couter10.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.547 ns counter10:inst1\|cout\[0\] 5 REG LCFF_X16_Y30_N23 5 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.547 ns; Loc. = LCFF_X16_Y30_N23; Fanout = 5; REG Node = 'counter10:inst1\|cout\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { counter10:inst1|cout~161 counter10:inst1|cout[0] } "NODE_NAME" } } { "couter10.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/couter10.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.917 ns ( 54.05 % ) " "Info: Total cell delay = 1.917 ns ( 54.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.630 ns ( 45.95 % ) " "Info: Total interconnect delay = 1.630 ns ( 45.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.547 ns" { enable:inst3|counter101[6] enable:inst3|always1~120 enable:inst3|always1~121 counter10:inst1|cout~161 counter10:inst1|cout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.547 ns" { enable:inst3|counter101[6] enable:inst3|always1~120 enable:inst3|always1~121 counter10:inst1|cout~161 counter10:inst1|cout[0] } { 0.000ns 0.512ns 0.386ns 0.732ns 0.000ns } { 0.000ns 0.651ns 0.624ns 0.534ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "in_28 destination 3.174 ns + Shortest register " "Info: + Shortest clock path from clock \"in_28\" to destination register is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns in_28 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'in_28'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { in_28 } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 104 144 312 120 "in_28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns in_28~clkctrl 2 COMB CLKCTRL_G3 17 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'in_28~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { in_28 in_28~clkctrl } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 104 144 312 120 "in_28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.666 ns) 3.174 ns counter10:inst1\|cout\[0\] 3 REG LCFF_X16_Y30_N23 5 " "Info: 3: + IC(1.179 ns) + CELL(0.666 ns) = 3.174 ns; Loc. = LCFF_X16_Y30_N23; Fanout = 5; REG Node = 'counter10:inst1\|cout\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.845 ns" { in_28~clkctrl counter10:inst1|cout[0] } "NODE_NAME" } } { "couter10.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/couter10.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.32 % ) " "Info: Total cell delay = 1.756 ns ( 55.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.418 ns ( 44.68 % ) " "Info: Total interconnect delay = 1.418 ns ( 44.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { in_28 in_28~clkctrl counter10:inst1|cout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { in_28 in_28~combout in_28~clkctrl counter10:inst1|cout[0] } { 0.000ns 0.000ns 0.239ns 1.179ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "in_28 source 3.176 ns - Longest register " "Info: - Longest clock path from clock \"in_28\" to source register is 3.176 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns in_28 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'in_28'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { in_28 } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 104 144 312 120 "in_28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns in_28~clkctrl 2 COMB CLKCTRL_G3 17 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'in_28~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { in_28 in_28~clkctrl } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 104 144 312 120 "in_28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.181 ns) + CELL(0.666 ns) 3.176 ns enable:inst3\|counter101\[6\] 3 REG LCFF_X17_Y30_N11 9 " "Info: 3: + IC(1.181 ns) + CELL(0.666 ns) = 3.176 ns; Loc. = LCFF_X17_Y30_N11; Fanout = 9; REG Node = 'enable:inst3\|counter101\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.847 ns" { in_28~clkctrl enable:inst3|counter101[6] } "NODE_NAME" } } { "enable.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/enable.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.29 % ) " "Info: Total cell delay = 1.756 ns ( 55.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.420 ns ( 44.71 % ) " "Info: Total interconnect delay = 1.420 ns ( 44.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { in_28 in_28~clkctrl enable:inst3|counter101[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { in_28 in_28~combout in_28~clkctrl enable:inst3|counter101[6] } { 0.000ns 0.000ns 0.239ns 1.181ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { in_28 in_28~clkctrl counter10:inst1|cout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { in_28 in_28~combout in_28~clkctrl counter10:inst1|cout[0] } { 0.000ns 0.000ns 0.239ns 1.179ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { in_28 in_28~clkctrl enable:inst3|counter101[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { in_28 in_28~combout in_28~clkctrl enable:inst3|counter101[6] } { 0.000ns 0.000ns 0.239ns 1.181ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "enable.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/enable.v" 8 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "couter10.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/couter10.v" 7 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.547 ns" { enable:inst3|counter101[6] enable:inst3|always1~120 enable:inst3|always1~121 counter10:inst1|cout~161 counter10:inst1|cout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.547 ns" { enable:inst3|counter101[6] enable:inst3|always1~120 enable:inst3|always1~121 counter10:inst1|cout~161 counter10:inst1|cout[0] } { 0.000ns 0.512ns 0.386ns 0.732ns 0.000ns } { 0.000ns 0.651ns 0.624ns 0.534ns 0.108ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { in_28 in_28~clkctrl counter10:inst1|cout[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { in_28 in_28~combout in_28~clkctrl counter10:inst1|cout[0] } { 0.000ns 0.000ns 0.239ns 1.179ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.176 ns" { in_28 in_28~clkctrl enable:inst3|counter101[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.176 ns" { in_28 in_28~combout in_28~clkctrl enable:inst3|counter101[6] } { 0.000ns 0.000ns 0.239ns 1.181ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "in_28 out counter11:inst5\|out11 9.188 ns register " "Info: tco from clock \"in_28\" to destination pin \"out\" through register \"counter11:inst5\|out11\" is 9.188 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "in_28 source 3.174 ns + Longest register " "Info: + Longest clock path from clock \"in_28\" to source register is 3.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.090 ns) 1.090 ns in_28 1 CLK PIN_M1 1 " "Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'in_28'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { in_28 } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 104 144 312 120 "in_28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.239 ns) + CELL(0.000 ns) 1.329 ns in_28~clkctrl 2 COMB CLKCTRL_G3 17 " "Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'in_28~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.239 ns" { in_28 in_28~clkctrl } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 104 144 312 120 "in_28" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.666 ns) 3.174 ns counter11:inst5\|out11 3 REG LCFF_X16_Y30_N29 2 " "Info: 3: + IC(1.179 ns) + CELL(0.666 ns) = 3.174 ns; Loc. = LCFF_X16_Y30_N29; Fanout = 2; REG Node = 'counter11:inst5\|out11'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.845 ns" { in_28~clkctrl counter11:inst5|out11 } "NODE_NAME" } } { "counter11.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/counter11.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.756 ns ( 55.32 % ) " "Info: Total cell delay = 1.756 ns ( 55.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.418 ns ( 44.68 % ) " "Info: Total interconnect delay = 1.418 ns ( 44.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { in_28 in_28~clkctrl counter11:inst5|out11 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { in_28 in_28~combout in_28~clkctrl counter11:inst5|out11 } { 0.000ns 0.000ns 0.239ns 1.179ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "counter11.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/counter11.v" 3 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.710 ns + Longest register pin " "Info: + Longest register to pin delay is 5.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter11:inst5\|out11 1 REG LCFF_X16_Y30_N29 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y30_N29; Fanout = 2; REG Node = 'counter11:inst5\|out11'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { counter11:inst5|out11 } "NODE_NAME" } } { "counter11.v" "" { Text "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/counter11.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.624 ns) 1.079 ns inst6 2 COMB LCCOMB_X16_Y30_N8 1 " "Info: 2: + IC(0.455 ns) + CELL(0.624 ns) = 1.079 ns; Loc. = LCCOMB_X16_Y30_N8; Fanout = 1; COMB Node = 'inst6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.079 ns" { counter11:inst5|out11 inst6 } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 144 680 744 192 "inst6" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.425 ns) + CELL(3.206 ns) 5.710 ns out 3 PIN PIN_F9 0 " "Info: 3: + IC(1.425 ns) + CELL(3.206 ns) = 5.710 ns; Loc. = PIN_F9; Fanout = 0; PIN Node = 'out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.631 ns" { inst6 out } "NODE_NAME" } } { "fen_pin_10_1.bdf" "" { Schematic "E:/FPGA/xinkaifabanshiyan/zijizuode/fenpin/fen_pin_10_1.bdf" { { 120 768 944 136 "out" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.830 ns ( 67.08 % ) " "Info: Total cell delay = 3.830 ns ( 67.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.880 ns ( 32.92 % ) " "Info: Total interconnect delay = 1.880 ns ( 32.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.710 ns" { counter11:inst5|out11 inst6 out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.710 ns" { counter11:inst5|out11 inst6 out } { 0.000ns 0.455ns 1.425ns } { 0.000ns 0.624ns 3.206ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.174 ns" { in_28 in_28~clkctrl counter11:inst5|out11 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.174 ns" { in_28 in_28~combout in_28~clkctrl counter11:inst5|out11 } { 0.000ns 0.000ns 0.239ns 1.179ns } { 0.000ns 1.090ns 0.000ns 0.666ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.710 ns" { counter11:inst5|out11 inst6 out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.710 ns" { counter11:inst5|out11 inst6 out } { 0.000ns 0.455ns 1.425ns } { 0.000ns 0.624ns 3.206ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 27 09:39:27 2007 " "Info: Processing ended: Thu Dec 27 09:39:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}