fen_pin_10_1.flow.rpt

利用verilog语言

Flow report for fen_pin_10_1
Thu Dec 27 09:39:33 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Flow Summary                                                                  ;
+------------------------------------+------------------------------------------+
; Flow Status                        ; Successful - Thu Dec 27 09:39:33 2007    ;
; Quartus II Version                 ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name                      ; fen_pin_10_1                             ;
; Top-level Entity Name              ; fen_pin_10_1                             ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35F484C8                             ;
; Timing Models                      ; Final                                    ;
; Met timing requirements            ; Yes                                      ;
; Total logic elements               ; 33 / 33,216 ( < 1 % )                    ;
; Total registers                    ; 17                                       ;
; Total pins                         ; 4 / 322 ( 1 % )                          ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0 / 483,840 ( 0 % )                      ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/27/2007 09:38:10 ;
; Main task         ; Compilation         ;
; Revision Name     ; fen_pin_10_1        ;
+-------------------+---------------------+


+--------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                           ;
+------------------------+--------------------+---------------+-------------+----------------+
; Assignment Name        ; Value              ; Default Value ; Entity Name ; Section Id     ;
+------------------------+--------------------+---------------+-------------+----------------+
; EDA_OUTPUT_DATA_FORMAT ; Verilog            ; --            ; --          ; eda_simulation ;
; EDA_SIMULATION_TOOL    ; ModelSim (Verilog) ; <None>        ; --          ; --             ;
; EDA_TIME_SCALE         ; 1 ps               ; --            ; --          ; eda_simulation ;
+------------------------+--------------------+---------------+-------------+----------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:03     ;
; Fitter               ; 00:00:29     ;
; Assembler            ; 00:00:26     ;
; Timing Analyzer      ; 00:00:01     ;
; EDA Netlist Writer   ; 00:00:03     ;
; Total                ; 00:01:02     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1
quartus_fit --read_settings_files=off --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1
quartus_asm --read_settings_files=off --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1
quartus_tan --read_settings_files=off --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1 --timing_analysis_only
quartus_eda --read_settings_files=off --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1