counter11.v

利用verilog语言

module counter11(out11,enable11,clk11);
input clk11,enable11;
output out11;
reg out11;
reg [3:0] cout11;
always @(posedge clk11)
if(enable11)  
   begin
    if (cout11==10)
       begin 
			out11=1'b1;
			cout11=1'b0;
	   end
	else 
		begin
			 out11=1'b0;
			 cout11=cout11+4'b0001;
		end
    end
else
   begin
		out11=0;
		cout11=0;
   end
endmodule