fen_pin_10_1.tan.rpt

利用verilog语言

; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; counter11:inst5|cout11[3]  ; counter11:inst5|out11      ; in_28      ; in_28    ; None                        ; None                      ; 1.655 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; enable:inst3|counter101[3] ; enable:inst3|counter101[4] ; in_28      ; in_28    ; None                        ; None                      ; 1.653 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; enable:inst3|counter101[2] ; enable:inst3|counter101[0] ; in_28      ; in_28    ; None                        ; None                      ; 1.591 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; enable:inst3|counter101[4] ; enable:inst3|counter101[4] ; in_28      ; in_28    ; None                        ; None                      ; 1.215 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; enable:inst3|counter101[1] ; enable:inst3|counter101[1] ; in_28      ; in_28    ; None                        ; None                      ; 1.174 ns                ;
; N/A   ; Restricted to 340.02 MHz ( period = 2.941 ns ) ; enable:inst3|counter101[3] ; enable:inst3|counter101[3] ; in_28      ; in_28    ; None                        ; None                      ; 1.174 ns                ;
+-------+------------------------------------------------+----------------------------+----------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+--------------------------------------------------------------------------------+
; tco                                                                            ;
+-------+--------------+------------+-----------------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From                  ; To    ; From Clock ;
+-------+--------------+------------+-----------------------+-------+------------+
; N/A   ; None         ; 9.188 ns   ; counter11:inst5|out11 ; out   ; in_28      ;
; N/A   ; None         ; 8.874 ns   ; counter10:inst1|out10 ; out   ; in_28      ;
; N/A   ; None         ; 8.651 ns   ; counter10:inst1|out10 ; out10 ; in_28      ;
; N/A   ; None         ; 8.190 ns   ; counter11:inst5|out11 ; out11 ; in_28      ;
+-------+--------------+------------+-----------------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Dec 27 09:39:26 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fen_pin_10_1 -c fen_pin_10_1 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "in_28" is an undefined clock
Info: Clock "in_28" has Internal fmax of 262.26 MHz between source register "enable:inst3|counter101[6]" and destination register "counter10:inst1|cout[0]" (period= 3.813 ns)
    Info: + Longest register to register delay is 3.547 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y30_N11; Fanout = 9; REG Node = 'enable:inst3|counter101[6]'
        Info: 2: + IC(0.512 ns) + CELL(0.651 ns) = 1.163 ns; Loc. = LCCOMB_X17_Y30_N22; Fanout = 1; COMB Node = 'enable:inst3|always1~120'
        Info: 3: + IC(0.386 ns) + CELL(0.624 ns) = 2.173 ns; Loc. = LCCOMB_X17_Y30_N26; Fanout = 6; COMB Node = 'enable:inst3|always1~121'
        Info: 4: + IC(0.732 ns) + CELL(0.534 ns) = 3.439 ns; Loc. = LCCOMB_X16_Y30_N22; Fanout = 1; COMB Node = 'counter10:inst1|cout~161'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 3.547 ns; Loc. = LCFF_X16_Y30_N23; Fanout = 5; REG Node = 'counter10:inst1|cout[0]'
        Info: Total cell delay = 1.917 ns ( 54.05 % )
        Info: Total interconnect delay = 1.630 ns ( 45.95 % )
    Info: - Smallest clock skew is -0.002 ns
        Info: + Shortest clock path from clock "in_28" to destination register is 3.174 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'in_28'
            Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'in_28~clkctrl'
            Info: 3: + IC(1.179 ns) + CELL(0.666 ns) = 3.174 ns; Loc. = LCFF_X16_Y30_N23; Fanout = 5; REG Node = 'counter10:inst1|cout[0]'
            Info: Total cell delay = 1.756 ns ( 55.32 % )
            Info: Total interconnect delay = 1.418 ns ( 44.68 % )
        Info: - Longest clock path from clock "in_28" to source register is 3.176 ns
            Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'in_28'
            Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'in_28~clkctrl'
            Info: 3: + IC(1.181 ns) + CELL(0.666 ns) = 3.176 ns; Loc. = LCFF_X17_Y30_N11; Fanout = 9; REG Node = 'enable:inst3|counter101[6]'
            Info: Total cell delay = 1.756 ns ( 55.29 % )
            Info: Total interconnect delay = 1.420 ns ( 44.71 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "in_28" to destination pin "out" through register "counter11:inst5|out11" is 9.188 ns
    Info: + Longest clock path from clock "in_28" to source register is 3.174 ns
        Info: 1: + IC(0.000 ns) + CELL(1.090 ns) = 1.090 ns; Loc. = PIN_M1; Fanout = 1; CLK Node = 'in_28'
        Info: 2: + IC(0.239 ns) + CELL(0.000 ns) = 1.329 ns; Loc. = CLKCTRL_G3; Fanout = 17; COMB Node = 'in_28~clkctrl'
        Info: 3: + IC(1.179 ns) + CELL(0.666 ns) = 3.174 ns; Loc. = LCFF_X16_Y30_N29; Fanout = 2; REG Node = 'counter11:inst5|out11'
        Info: Total cell delay = 1.756 ns ( 55.32 % )
        Info: Total interconnect delay = 1.418 ns ( 44.68 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.710 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X16_Y30_N29; Fanout = 2; REG Node = 'counter11:inst5|out11'
        Info: 2: + IC(0.455 ns) + CELL(0.624 ns) = 1.079 ns; Loc. = LCCOMB_X16_Y30_N8; Fanout = 1; COMB Node = 'inst6'
        Info: 3: + IC(1.425 ns) + CELL(3.206 ns) = 5.710 ns; Loc. = PIN_F9; Fanout = 0; PIN Node = 'out'
        Info: Total cell delay = 3.830 ns ( 67.08 % )
        Info: Total interconnect delay = 1.880 ns ( 32.92 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Dec 27 09:39:27 2007
    Info: Elapsed time: 00:00:01