couter10.v

利用verilog语言

module counter10(out10,enable10,clk10);
input clk10,enable10;
output out10;
reg out10;
reg [3:0] cout;
always @(posedge clk10)
if(enable10) 
   begin
   if (cout==9)
       begin 
			out10=1'b1;
			cout=1'b0;
	   end
	else 
		begin
			 out10=1'b0;
			 cout=cout+4'b0001;
		end
   end
else 
    begin
		out10=0;
		cout=0;
	end
endmodule