enable.v

利用verilog语言

module enable(outin,clk);
input clk;
output outin;
reg outin;
reg [6:0] counter101;
//
always @(posedge clk)
   if(counter101==100)
 		counter101=7'b0000000;
   else 
      counter101=counter101+7'b0000001;
//
always @(counter101)
   if((90<counter101)||(counter101==0))
      outin=1'b0;
   else 
      outin=1'b1;
//      
endmodule