dds.hif

利用VHDL语言实现在

Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
35
1763
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
DDS
# storage
db|dds.(0).cnf
db|dds.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
dds.vhd
1e51fdd0cd65fa1b53bf3d38ff4b861
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
ps7
# storage
db|dds.(1).cnf
db|dds.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
ps7.vhd
3514473c6d8efe9afa87486412dd487
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(count1)
8 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
ps7:u0
}
# end
# entity
ADDER7B
# storage
db|dds.(3).cnf
db|dds.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
adder7b.vhd
ea831ea3961ff15e2860179b223a99d8
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(a)
6 downto 0
PARAMETER_STRING
USR
 constraint(b)
6 downto 0
PARAMETER_STRING
USR
 constraint(s)
6 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DDS1:u1|ADDER7B:u1
DDS1:u1|ADDER7B:u4
}
# end
# entity
REG7B
# storage
db|dds.(4).cnf
db|dds.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
reg7b.vhd
22482192fe105bb1ae721c9d936512b2
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(din)
6 downto 0
PARAMETER_STRING
USR
 constraint(dout)
6 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DDS1:u1|REG7B:u2
DDS1:u1|REG7B:u5
}
# end
# entity
sin_rom
# storage
db|dds.(5).cnf
db|dds.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
SIN_ROM.VHD
c354571bb4f45210e3ff9521cf35bff2
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(address)
6 downto 0
PARAMETER_STRING
USR
 constraint(q)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DDS1:u1|sin_rom:u3
}
# end
# entity
altsyncram_hq21
# storage
db|dds.(7).cnf
db|dds.(7).cnf
# case_insensitive
# source_file
db|altsyncram_hq21.tdf
dd2fb046fc19e172eb4fcda7f1ab77
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sin7.mif
d22abf26e848bf5246b0ac93a0f516
}
# hierarchies {
DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_hq21:auto_generated
}
# end
# entity
PL_DPSK2
# storage
db|dds.(8).cnf
db|dds.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
pl_dpsk2.vhd
7a9dea153e833273cd4bc34a8afa0
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
PL_DPSK2:u2
}
# end
# entity
fangbo
# storage
db|dds.(9).cnf
db|dds.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
fangbo.vhd
6d5e92fcf55cbd741fb4fa1e389d3b66
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(fout)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
fangbo:u3
}
# end
# entity
DDS1
# storage
db|dds.(2).cnf
db|dds.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
DDS1.VHD
97237712caebf86593d34e9b1ec35ff
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
 constraint(dds_out)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
DDS1:u1
}
# end
# entity
altsyncram
# storage
db|dds.(6).cnf
db|dds.(6).cnf
# case_insensitive
# source_file
d:|program files|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
7
PARAMETER_DEC
USR
NUMWORDS_A
128
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin7.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hq21
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# include_file {
d:|program files|altera|quartus60|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
d:|program files|altera|quartus60|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
d:|program files|altera|quartus60|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
d:|program files|altera|quartus60|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
d:|program files|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
d:|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
d:|program files|altera|quartus60|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
d:|program files|altera|quartus60|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
d:|program files|altera|quartus60|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
d:|program files|altera|quartus60|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
}
# hierarchies {
DDS1:u1|sin_rom:u3|altsyncram:altsyncram_component
}
# end
# complete