dds.tan.qmsg

利用VHDL语言实现在

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register DDS1:u1\|P7B\[6\] register DDS1:u1\|REG7B:u5\|DOUT\[6\] 170.62 MHz 5.861 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 170.62 MHz between source register \"DDS1:u1\|P7B\[6\]\" and destination register \"DDS1:u1\|REG7B:u5\|DOUT\[6\]\" (period= 5.861 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.046 ns + Longest register register " "Info: + Longest register to register delay is 1.046 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS1:u1\|P7B\[6\] 1 REG LC_X9_Y13_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N8; Fanout = 2; REG Node = 'DDS1:u1\|P7B\[6\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DDS1:u1|P7B[6] } "NODE_NAME" } } { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.737 ns) + CELL(0.309 ns) 1.046 ns DDS1:u1\|REG7B:u5\|DOUT\[6\] 2 REG LC_X8_Y13_N9 1 " "Info: 2: + IC(0.737 ns) + CELL(0.309 ns) = 1.046 ns; Loc. = LC_X8_Y13_N9; Fanout = 1; REG Node = 'DDS1:u1\|REG7B:u5\|DOUT\[6\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.046 ns" { DDS1:u1|P7B[6] DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns ( 29.54 % ) " "Info: Total cell delay = 0.309 ns ( 29.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.737 ns ( 70.46 % ) " "Info: Total interconnect delay = 0.737 ns ( 70.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.046 ns" { DDS1:u1|P7B[6] DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.046 ns" { DDS1:u1|P7B[6] DDS1:u1|REG7B:u5|DOUT[6] } { 0.000ns 0.737ns } { 0.000ns 0.309ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.554 ns - Smallest " "Info: - Smallest clock skew is -4.554 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.211 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/dds.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns DDS1:u1\|REG7B:u5\|DOUT\[6\] 2 REG LC_X8_Y13_N9 1 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y13_N9; Fanout = 1; REG Node = 'DDS1:u1\|REG7B:u5\|DOUT\[6\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { CLK DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLK DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLK CLK~out0 DDS1:u1|REG7B:u5|DOUT[6] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.765 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/dds.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns DDS1:u1\|q\[8\] 2 REG LC_X8_Y13_N7 8 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 8; REG Node = 'DDS1:u1\|q\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { CLK DDS1:u1|q[8] } "NODE_NAME" } } { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.619 ns) + CELL(0.711 ns) 7.765 ns DDS1:u1\|P7B\[6\] 3 REG LC_X9_Y13_N8 2 " "Info: 3: + IC(3.619 ns) + CELL(0.711 ns) = 7.765 ns; Loc. = LC_X9_Y13_N8; Fanout = 2; REG Node = 'DDS1:u1\|P7B\[6\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.330 ns" { DDS1:u1|q[8] DDS1:u1|P7B[6] } "NODE_NAME" } } { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.12 % ) " "Info: Total cell delay = 3.115 ns ( 40.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.650 ns ( 59.88 % ) " "Info: Total interconnect delay = 4.650 ns ( 59.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.765 ns" { CLK DDS1:u1|q[8] DDS1:u1|P7B[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.765 ns" { CLK CLK~out0 DDS1:u1|q[8] DDS1:u1|P7B[6] } { 0.000ns 0.000ns 1.031ns 3.619ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLK DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLK CLK~out0 DDS1:u1|REG7B:u5|DOUT[6] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.765 ns" { CLK DDS1:u1|q[8] DDS1:u1|P7B[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.765 ns" { CLK CLK~out0 DDS1:u1|q[8] DDS1:u1|P7B[6] } { 0.000ns 0.000ns 1.031ns 3.619ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 50 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "reg7b.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/reg7b.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.046 ns" { DDS1:u1|P7B[6] DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "1.046 ns" { DDS1:u1|P7B[6] DDS1:u1|REG7B:u5|DOUT[6] } { 0.000ns 0.737ns } { 0.000ns 0.309ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLK DDS1:u1|REG7B:u5|DOUT[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLK CLK~out0 DDS1:u1|REG7B:u5|DOUT[6] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.765 ns" { CLK DDS1:u1|q[8] DDS1:u1|P7B[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.765 ns" { CLK CLK~out0 DDS1:u1|q[8] DDS1:u1|P7B[6] } { 0.000ns 0.000ns 1.031ns 3.619ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK din1 ps7:u0\|q 12.732 ns register " "Info: tco from clock \"CLK\" to destination pin \"din1\" through register \"ps7:u0\|q\" is 12.732 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.765 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 7.765 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/dds.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns DDS1:u1\|q\[8\] 2 REG LC_X8_Y13_N7 8 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N7; Fanout = 8; REG Node = 'DDS1:u1\|q\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.966 ns" { CLK DDS1:u1|q[8] } "NODE_NAME" } } { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.619 ns) + CELL(0.711 ns) 7.765 ns ps7:u0\|q 3 REG LC_X9_Y13_N5 2 " "Info: 3: + IC(3.619 ns) + CELL(0.711 ns) = 7.765 ns; Loc. = LC_X9_Y13_N5; Fanout = 2; REG Node = 'ps7:u0\|q'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.330 ns" { DDS1:u1|q[8] ps7:u0|q } "NODE_NAME" } } { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/ps7.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.12 % ) " "Info: Total cell delay = 3.115 ns ( 40.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.650 ns ( 59.88 % ) " "Info: Total interconnect delay = 4.650 ns ( 59.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.765 ns" { CLK DDS1:u1|q[8] ps7:u0|q } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.765 ns" { CLK CLK~out0 DDS1:u1|q[8] ps7:u0|q } { 0.000ns 0.000ns 1.031ns 3.619ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/ps7.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.743 ns + Longest register pin " "Info: + Longest register to pin delay is 4.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ps7:u0\|q 1 REG LC_X9_Y13_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N5; Fanout = 2; REG Node = 'ps7:u0\|q'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ps7:u0|q } "NODE_NAME" } } { "ps7.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/ps7.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.635 ns) + CELL(2.108 ns) 4.743 ns din1 2 PIN PIN_225 0 " "Info: 2: + IC(2.635 ns) + CELL(2.108 ns) = 4.743 ns; Loc. = PIN_225; Fanout = 0; PIN Node = 'din1'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.743 ns" { ps7:u0|q din1 } "NODE_NAME" } } { "dds.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/dds.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 44.44 % ) " "Info: Total cell delay = 2.108 ns ( 44.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.635 ns ( 55.56 % ) " "Info: Total interconnect delay = 2.635 ns ( 55.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.743 ns" { ps7:u0|q din1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.743 ns" { ps7:u0|q din1 } { 0.000ns 2.635ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.765 ns" { CLK DDS1:u1|q[8] ps7:u0|q } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "7.765 ns" { CLK CLK~out0 DDS1:u1|q[8] ps7:u0|q } { 0.000ns 0.000ns 1.031ns 3.619ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.743 ns" { ps7:u0|q din1 } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.743 ns" { ps7:u0|q din1 } { 0.000ns 2.635ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "CLK count1\[8\] DDS1:u1\|q\[8\] 7.766 ns register " "Info: Minimum tco from clock \"CLK\" to destination pin \"count1\[8\]\" through register \"DDS1:u1\|q\[8\]\" is 7.766 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.211 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to source register is 3.211 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK 1 CLK PIN_28 43 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 43; CLK Node = 'CLK'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "dds.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/dds.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.711 ns) 3.211 ns DDS1:u1\|q\[8\] 2 REG LC_X8_Y13_N7 8 " "Info: 2: + IC(1.031 ns) + CELL(0.711 ns) = 3.211 ns; Loc. = LC_X8_Y13_N7; Fanout = 8; REG Node = 'DDS1:u1\|q\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.742 ns" { CLK DDS1:u1|q[8] } "NODE_NAME" } } { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 67.89 % ) " "Info: Total cell delay = 2.180 ns ( 67.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.031 ns ( 32.11 % ) " "Info: Total interconnect delay = 1.031 ns ( 32.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLK DDS1:u1|q[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLK CLK~out0 DDS1:u1|q[8] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.331 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS1:u1\|q\[8\] 1 REG LC_X8_Y13_N7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y13_N7; Fanout = 8; REG Node = 'DDS1:u1\|q\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { DDS1:u1|q[8] } "NODE_NAME" } } { "DDS1.VHD" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/DDS1.VHD" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.207 ns) + CELL(2.124 ns) 4.331 ns count1\[8\] 2 PIN PIN_23 0 " "Info: 2: + IC(2.207 ns) + CELL(2.124 ns) = 4.331 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'count1\[8\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.331 ns" { DDS1:u1|q[8] count1[8] } "NODE_NAME" } } { "dds.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/psk_mc/dds.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 49.04 % ) " "Info: Total cell delay = 2.124 ns ( 49.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.207 ns ( 50.96 % ) " "Info: Total interconnect delay = 2.207 ns ( 50.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.331 ns" { DDS1:u1|q[8] count1[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.331 ns" { DDS1:u1|q[8] count1[8] } { 0.000ns 2.207ns } { 0.000ns 2.124ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.211 ns" { CLK DDS1:u1|q[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.211 ns" { CLK CLK~out0 DDS1:u1|q[8] } { 0.000ns 0.000ns 1.031ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.331 ns" { DDS1:u1|q[8] count1[8] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "4.331 ns" { DDS1:u1|q[8] count1[8] } { 0.000ns 2.207ns } { 0.000ns 2.124ns } } }  } 0 0 "Minimum tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 25 10:42:41 2007 " "Info: Processing ended: Mon Jun 25 10:42:41 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}