dds.vhd

来自「利用VHDL语言实现在」· VHDL 代码 · 共 44 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DDS IS                                     -- 顶层设计
    PORT (     CLK : IN  STD_LOGIC;
                dds_out:out std_logic_vector(7 downto 0);
                 dc_out:out std_logic; 
                count1:out std_logic_vector(8 downto 0) ;
                ls:in std_logic ;         --接收端解调输出的信号
                din1:out std_logic
               );                --发送端输入的信号
 END;
ARCHITECTURE one OF DDS IS
component ps7 is
port(clk:in std_logic;
load:in std_logic;
 q:out std_logic;
count1:out std_logic_vector(8 downto 0) );
end component;
component dds1            
PORT (     CLK : IN  STD_LOGIC;
               dds_out:out std_logic_vector(7 downto 0);
          din :in std_logic);
 END component;
component fangbo IS                                     --将接收到的信号整形成方波
    PORT (     clk : IN  STD_LOGIC; 
              fout : in STD_LOGIC_VECTOR(7 DOWNTO 0);
                 y : out std_logic );
    end component fangbo;
component pl_dpsk2
port (clk    :in std_logic;          --系统时钟
     x    :in std_logic;       --方波输入信号
     y    :out std_logic);     --绝对码输出信号
end component PL_DPSK2;
signal r_dds:std_logic_VECTOR(7 DOWNTO 0);--基于DDS的2PSK信号
signal r_fb: STD_LOGIC; --将DDS整形后的方波信号
signal din :std_logic;
begin
u0:ps7 port map(clk,ls,din,count1);
u1:dds1 port map(clk,r_dds,din);    --发送端产生DDS的2PSK信号
u2:pl_dpsk2 port map(clk,r_fb,dc_out); --将整形后的方波信号解调
u3:fangbo port map(clk=>clk,fout=>r_dds,y=>r_fb);--将发送端产生的DDS信号整形成方波
dds_out<=r_dds;din1<=din;
end;