dds.tan.summary

利用VHDL语言实现在

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.732 ns
From           : ps7:u0|q
To             : din1
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 7.766 ns
From           : DDS1:u1|q[8]
To             : count1[8]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 170.62 MHz ( period = 5.861 ns )
From           : DDS1:u1|P7B[6]
To             : DDS1:u1|REG7B:u5|DOUT[6]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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