freqdivfinal.vhd

用vhdl实现的分频器

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:55:38 10/31/2007 
-- Design Name: 
-- Module Name:    freqdivfinal - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity freqdivfinal is
port(
		clk,nwr:in std_logic;
		cs:in std_logic_vector(3 downto 0);
		data:in std_logic_vector(7 downto 0);
		clkout:out std_logic_vector(3 downto 0);
		clko:out std_logic
		);
end freqdivfinal;

architecture Behavioral of freqdivfinal is


--signal declearation
type DATALEN is array (3 downto 0) of std_logic_vector(6 downto 0);
type PULSENUM is array(3 downto 0) of std_logic_vector(15 downto 0);
--dividing value
signal divvalue:DATALEN ;
--number of pulse needed
signal pulnum:PULSENUM;
--20K ,1M Hz ,1K basic clock
signal clktemplk,clktempnk,clktemponek:std_logic :='0';
--channel control
signal chnlsel:std_logic_vector(1 downto 0);
--output control
signal chnlctr:std_logic_vector(3 downto 0) :="1111";
signal clktemp,clknk:std_logic_vector(3 downto 0) :="0000";
--flagclk:choose 1k or 100k Hz clock
--flag:number of pulse is enough or not 
signal flag,flagclk:std_logic_vector(3 downto 0);
--whether or not starting temporary clock 
-------------
--clk:MCK 45M Hz
begin

--generate 1kHz clock
process(clktemplk)
variable countb:std_logic_vector(3 downto 0) :="0000";
begin
		if(rising_edge(clktemplk))then
				if(countb="1001")then
						clktemponek<=not clktemponek;
						countb:=(others=>'0');
				else
						countb:=countb+1;
				end if;
				clko<=clktemponek;
		end if;
end process;
		
--generate 20kHz clock
process(clktempnk)
variable counta:std_logic_vector(4 downto 0) :="00000";
begin		
		if(rising_edge(clktempnk))then				
				if(counta="11000")then
						counta:="00000";
						clktemplk<=not clktemplk;
				else
						counta:=counta+1;
				end if;
		end if;
end process;	

--generate 1M Hz  clock
process(clk)
variable count:std_logic_vector(5 downto 0):="000000";	
begin		
		if(rising_edge(clk))then			
				if(count="101100")then
						count:=(others=>'0');
						clktempnk<='1';
				else
						count:=count+1;
						clktempnk<='0';
				end if;
		end if;
end process;		

--select function
process(nwr,clk)
begin		
		if(rising_edge(clk))then	
			if(nwr='0')then	
				if(cs(0)='0')then
						if(data(6 downto 5)="00")then								
								chnlsel<=data(1 downto 0);	
						elsif(data(6 downto 5)="01")then
								case data(1 downto 0) is 
										when "00"=>chnlctr(0)<=data(7);
										when "01"=>chnlctr(1)<=data(7);
										when "10"=>chnlctr(2)<=data(7);
										when "11"=>chnlctr(3)<=data(7);
										when others=>null;
								end case;
						else
								null;
						end if;
				elsif(cs(1)='0')then
						case chnlsel is
								when "00"=>
										flagclk(0)<=data(7);
										divvalue(0)<=data(6 downto 0);
								when "01"=>
										flagclk(1)<=data(7);
										divvalue(1)<=data(6 downto 0);
								when "10"=>
										flagclk(2)<=data(7);
										divvalue(2)<=data(6 downto 0);
								when "11"=>
										flagclk(3)<=data(7);
										divvalue(3)<=data(6 downto 0);
								when others=>null;
						end case;
				elsif(cs(2)='0')then
						case chnlsel is
								when "00"=>pulnum(0)(7 downto 0)<=data;
								when "01"=>pulnum(1)(7 downto 0)<=data;
								when "10"=>pulnum(2)(7 downto 0)<=data;
								when "11"=>pulnum(3)(7 downto 0)<=data;
								when others=>null;
						end case;
				elsif(cs(3)='0')then
						case chnlsel is
								when "00"=>pulnum(0)(15 downto 8)<=data;
								when "01"=>pulnum(1)(15 downto 8)<=data;
								when "10"=>pulnum(2)(15 downto 8)<=data;
								when "11"=>pulnum(3)(15 downto 8)<=data;
								when others=>null;
						end case;
				end if;	
			end if;	
		end if;
end process;	
--select corresponding  clock
process(clk,flagclk)
begin
		if(rising_edge(clk))then		
				if(flagclk(0)='0')then
						clknk(0)<=clktemplk;
				else
						clknk(0)<=clktempnk;
				end if;
				if(flagclk(1)='0')then
						clknk(1)<=clktemplk;
				else
						clknk(1)<=clktempnk;
				end if;
				if(flagclk(2)='0')then
						clknk(2)<=clktemplk;
				else
						clknk(2)<=clktempnk;
				end if;								
				if(flagclk(3)='0')then
						clknk(3)<=clktemplk;
				else
						clknk(3)<=clktempnk;
				end if;
		end if;		
end process;
								
--generate temporary clock
process(clknk(0),chnlctr(0))
variable divtempa:std_logic_vector(6 downto 0):="0000001";
begin		
		if(clknk(0)'event)then
			if(chnlctr(0)='0')then
				if(divtempa=divvalue(0))then
						divtempa:="0000001";
						clktemp(0)<=not clktemp(0);
				else
						divtempa:=divtempa+1;
				end if;
			end if;	
		end if;
end process;	

process(clknk(1),chnlctr(1))
variable divtempb:std_logic_vector(6 downto 0) :="0000001";
begin		
		if(clknk(1)'event)then				
			if(chnlctr(1)='0')then	
				if(divtempb=divvalue(1))then
						divtempb:="0000001";
						clktemp(1)<=not clktemp(1);
				else
						divtempb:=divtempb+1;
				end if;
			end if;	
		end if;
end process;	

process(clknk(2),chnlctr(2))
variable divtempc:std_logic_vector(6 downto 0):="0000001";
begin		
		if(clknk(2)'event)then			
			if(chnlctr(2)='0')then	
				if(divtempc=divvalue(2))then
						divtempc:="0000001";
						clktemp(2)<=not clktemp(2);
				else
						divtempc:=divtempc+1;
				end if;
			end if;	
		end if;
end process;	

process(clknk(3),chnlctr(3))
variable divtempd:std_logic_vector(6 downto 0):="0000001";
begin		
		if(clknk(3)'event)then
			if(chnlctr(3)='0')then	
				if(divtempd=divvalue(3))then
						divtempd:="0000001";
						clktemp(3)<=not clktemp(3);
				else
						divtempd:=divtempd+1;
				end if;
			end if;	
		end if;
end process;	
	
--count pulse
process(clktemp(0),chnlctr(0))
variable pultempa:std_logic_vector(15 downto 0);
begin		
		if(chnlctr(0)='1')then
				pultempa:=(others=>'0');
		elsif(rising_edge(clktemp(0)))then
				if(pulnum(0)="0000000000000000")then
						flag(0)<='0';
				elsif(pultempa=pulnum(0))then
						flag(0)<='1';
				else
						pultempa:=pultempa+1;
						flag(0)<='0';
				end if;
		end if;
end process;		
				
process(clktemp(1),chnlctr(1))
variable pultempb:std_logic_vector(15 downto 0);
begin		
		if(chnlctr(1)='1')then
				pultempb:=(others=>'0');
		elsif(rising_edge(clktemp(1)))then
				if(pulnum(1)="0000000000000000")then
						flag(1)<='0';
				elsif(pultempb=pulnum(1))then
						flag(1)<='1';
				else
						pultempb:=pultempb+1;
						flag(1)<='0';
				end if;
		end if;
end process;	

process(clktemp(2),chnlctr(2))
variable pultempc:std_logic_vector(15 downto 0);
begin		
		if(chnlctr(2)='1')then
				pultempc:=(others=>'0');
		elsif(rising_edge(clktemp(2)))then
				if(pulnum(2)="0000000000000000")then
						flag(2)<='0';
				elsif(pultempc=pulnum(2))then
						flag(2)<='1';
				else
						pultempc:=pultempc+1;
						flag(2)<='0';
				end if;
		end if;
end process;	

process(clktemp(3),chnlctr(3))
variable pultempd:std_logic_vector(15 downto 0);	
begin		
		if(chnlctr(3)='1')then
				pultempd:=(others=>'0');
		elsif(rising_edge(clktemp(3)))then
				if(pulnum(3)="0000000000000000")then
						flag(3)<='0';
				elsif(pultempd=pulnum(3))then
						flag(3)<='1';
				else
						pultempd:=pultempd+1;
						flag(3)<='0';
				end if;
		end if;
end process;		

--output clock
process(clk,chnlctr,flag)
begin		
		if(rising_edge(clk))then				
				for i in 3 downto 0 loop
						if(chnlctr(i)='0')then
								if(flag(i)='0')then
										clkout(i)<=clktemp(i);
								else
										clkout(i)<='0';
								end if;
						else
								clkout(i)<='0';
						end if;		
				end loop;
		end if;
end process;					


end Behavioral;