crc_3.v

循环码编码器verilog实现

module crc_3(rest,clk,start,Din,Vout);
parameter size=4;//the length of initial signal
parameter with=3;//the length of generator    
input rest,clk;
input[size-1:0] Din;//initial signal
output[size+with-1:0]Vout;//????
reg[size+with-1:0] Vout;
reg Dx;
wire Vx;
reg en_out;
//******************************************************/
//??????   
//******************************************************/
parameter  rdy=7'b1000000,
          bit3=7'b0100000,
          bit2=7'b0010000,
          bit1=7'b0001000,
          bit0=7'b0000100,
         bit_1=7'b0000010,
         bit_2=7'b0000001;
 reg[6:0]in_state; 
 input start;        
 always@(posedge clk or negedge rest) 
     if(!rest)
          begin
           in_state<=rdy;
           Dx<=1'b0;
           en_out<=0;
          end   
     else 
         if(start)
         case(in_state)
         rdy:  begin
               in_state<=bit3;
               Dx<=Din[3];
               en_out<=1;
               end    
         bit3: begin
               in_state<=bit2;
               Dx<=Din[2];
               en_out<=0;
               end 
         bit2: begin
               in_state<=bit1;
               Dx<=Din[1];
               en_out<=0;
               end 
         bit1: begin
               in_state<=bit0;
               Dx<=Din[0];
               en_out<=0;
               end  
         bit0: begin
               in_state<=bit_1;
               Dx<=1'b0;
               en_out<=0;
               end  
         bit_1: begin
               in_state<=bit_2;
               Dx<=1'b0;
               en_out<=0;
               end      
               
         bit_2: begin
               in_state<=rdy;
               Dx<=1'b0;
               en_out<=0;
               end          
                                                    
        default: begin
                 in_state<=rdy;
                 Dx<=1'b0;
                 en_out<=0;
                 end       
        endcase          
   //-----------------------------------------------------------
   //LFSR?????????
   //-----------------------------------------------------------
    reg[with-1:0]lfsr;
    integer i;
    parameter tap=3'b010;
    always@(posedge clk or negedge rest)
        if(!rest)
          lfsr<=0;
        else 
            begin
               for(i=0;i<=with-1;i=i+1) 
                 if(tap[i])
                     lfsr[i]<=lfsr[i-1]^Dx;
                 else lfsr[i]<=lfsr[i-1];
               lfsr[0]<=Dx;  
            end 
    assign Vx=Dx^lfsr[with-1] ;
    //---------------------------------------------------------------
    //???????????
    //--------------------------------------------------------------
    reg[size+with-1:0]V_out;
    always@ (posedge clk or negedge rest)
        if(~rest)
         V_out<=1'bz;
        else
           begin
           V_out<= V_out<<1;
           V_out[0]<=Vx;
           end
    always@(en_out)
         if(en_out) 
          Vout<= V_out; 
 endmodule