seg7_1a.map.qmsg

输入一个四位二进制数

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 10 11:12:57 2006 " "Info: Processing started: Mon Apr 10 11:12:57 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off seg7_1a -c seg7_1a " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off seg7_1a -c seg7_1a" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_1a.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_1a.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_1a-seg7_1a_arch " "Info: Found design unit 1: seg7_1a-seg7_1a_arch" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "seg7_1a-seg7_1a_arch" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_1a " "Info: Found entity 1: seg7_1a" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "seg7_1a" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "seg7_1.vhd 2 1 " "Info: Using design file seg7_1.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_1-seg7_1_arch " "Info: Found design unit 1: seg7_1-seg7_1_arch" {  } { { "g:/study/experience/新建文件夹/seg7_1.vhd" "seg7_1-seg7_1_arch" "" { Text "g:/study/experience/新建文件夹/seg7_1.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_1 " "Info: Found entity 1: seg7_1" {  } { { "g:/study/experience/新建文件夹/seg7_1.vhd" "seg7_1" "" { Text "g:/study/experience/新建文件夹/seg7_1.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg7_1.vhd(30) " "Info: VHDL Case Statement information at seg7_1.vhd(30): OTHERS choice is never selected" {  } { { "g:/study/experience/新建文件夹/seg7_1.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1.vhd" 30 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "cat\[5\] VCC " "Warning: Pin cat\[5\] stuck at VCC" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cat\[4\] VCC " "Warning: Pin cat\[4\] stuck at VCC" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cat\[3\] VCC " "Warning: Pin cat\[3\] stuck at VCC" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cat\[2\] VCC " "Warning: Pin cat\[2\] stuck at VCC" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cat\[1\] VCC " "Warning: Pin cat\[1\] stuck at VCC" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 8 -1 0 } }  } 0} { "Warning" "WOPT_MLS_STUCK_PIN" "cat\[0\] GND " "Warning: Pin cat\[0\] stuck at GND" {  } { { "g:/study/experience/新建文件夹/seg7_1a.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1a.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "17 " "Info: Implemented 17 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 10 11:12:59 2006 " "Info: Processing ended: Mon Apr 10 11:12:59 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}