seg7_1.vhd

来自「输入一个四位二进制数」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.std_logic_1164.all;
entity seg7_1 is
   port(
      a:in STD_LOGIC_VECTOR(3 downto 0);
      b:out STD_LOGIC_VECTOR(6 downto 0)
   );
end seg7_1;
architecture seg7_1_arch of seg7_1 is
begin
   process(a)
   begin 
      case a is
        when"0000"=>b<="1111110";--0
        when"0001"=>b<="0110000";--1  
        when"0010"=>b<="1101101";--2
        when"0011"=>b<="1111001";--3
        when"0100"=>b<="0110011";--4
        when"0101"=>b<="1011011";--5
        when"0110"=>b<="1011111";--6
        when"0111"=>b<="1110000";--7
        when"1000"=>b<="1111111";--8
        when"1001"=>b<="1111011";--9
        when"1010"=>b<="0000000";
        when"1011"=>b<="0000000";
        when"1100"=>b<="0000000";
        when"1101"=>b<="0000000";
        when"1110"=>b<="0000000";
        when"1111"=>b<="0000000";
        when others=>b<="0000000";
     end case;
end process;
end;